Z80382 Datasheet, PDF (68/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued)
System Configuration Register
The System Configuration Register controls the major
modes of the Z382:
s How pins 60 - 92 are used:
Ð connected to the ISA bus of a host PC;
Ð connected to the PCMCIA bus of a host PC;
Ð used for the ASCIs, CSI/O, and ports A and D,
except that the full-time outputs among these
signals (TXA0, TXA1, RTS0, TxS) are disabled;
Ð used for the ASCIs, CSI/O, and ports A and D,
including the TXA0, TXA1, RTS0, and TxS
outputs.
s How pins 110-112 are used:
Ð /DCD0, /CTS0, /CTS1 ASCI control signals;
Ð TREFA, TREFC, and TREFR DRAM control
signals.
s D15 - 0 use during reads from on-chip I/O devices:
Ð the D15-0 pins are driven as outputs from the
Z382;
Ð the pins are left tri-stated to reduce power
consumption, noise, and EMI/RFI to some extent.
s I/O address decoding of the Mimic and Parallel Ports:
Ð A15-8 must be zero to access these features;
Ð the address decoding for these ports disregards
address lines above A7, so that these devices are
replicated in each 256-byte ÒpageÓ of I/O space as
on the Z80182, 187, and 189.
s The relative interrupt priority of the Mimic, HDLC
channels, and DMA channels on the INT0 daisy chain.
In addition to the control above, certain pins are multi-
plexed automatically based on the state of register bits in
their associated functions.
Pin Multiplexing Register
The Pin Multiplexing Register controls smaller-scale pin
multiplexing issues than those handled in the System Con-
figuration Register.
s Whether the pins normally used for HDLC 0 are used for
ASCI0 signals instead.
s Whether the pins normally used for HDLC 1 are used for
ASCI1 signals instead.
s The functions of pins 47, 48, 49, 53, 56, 57, 58 and 109.
Programable Low Noise Drivers
To help reduce noise generated by the output switching of
the Z382, selected outputs can be placed in a reduced
drive configuration. When a pin is placed in low noise
mode, its drive is reduced to 1/3 of its normal output drive
current. This decreases the slew rate of the driver, which
reduces current spikes induced onto the power bussing of
the Z382.
The Output Drive Control Register provides this function
for a number of groups of Z382 output or I/O pins.
68
PRELIMINARY
DS97Z382000