Z80382 Datasheet, PDF (66/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued)
Interrupt Registers
The following I/O-mapped registers are associated with in-
terrupts and can be read and written by the 380C proces-
sor:
s Interrupt Enable Register
s Assigned Vectors Base Register
s INT3-1 Control Register
s Trap and Break Register
Interrupt Enable Register. Provides the current status of
the /INT3-0 pins and controls whether /INT3, /INT2, /INT1,
and /INT0 are enabled or disabled. Note that these flags
are also affected by enable and disable interrupt instruc-
tions (DI (n) and EI (n)).
Assigned Vectors Base Register. The Interrupt Register
Extension, Iz, together with the contents in bits 1-7 of this
register, define the base address of the assigned interrupt
vectors table in memory space.
INT3-1 Control Register. Controls when and how the
Z382 recognizes an interrupt on the corresponding pins
(High or Low Level sensitive, Falling or Rising Edge Trig-
gered) and provides the means for clearing edge triggered
interrupt requests if such are specified for /INT3-1.
Trap and Break Register. Two bits of this register provide
status on traps. One bit is set if an undefined opcode is
fetched in the instruction stream. A second bit is set if an
undefined opcode is returned as a vector in an interrupt ac-
knowledge transaction in mode 0.
Z380-Compatible Peripheral Functions
The Z382 incorporates a number of Z80380 compatible
functions. The Z382Õs I/O bus can be programmed to run
at a slower rate than its memory bus. In addition, a heart-
beat transaction can be generated on the I/O bus that em-
ulates a Z80 instruction fetch cycle. Such cycles are need-
ed for a particular Z80 family I/O device to perform its
interrupt functions. Finally, a DRAM refresh function is in-
corporated, with programmable refresh transaction burst
size.
I/O Bus Control
The Z382 is designed to interface easily with external I/O
devices that can be of either the Z80 or Z8500 product
family by supplying four I/O bus control signals: /M1,
/IORQ, /IORD, and /IOWR. In addition, the Z382 supplies
an IOCLK that is a divided down version of its BUSCLK.
Programmable wait states can be inserted in the various
I/O transactions.
DRAM Refresh
The Z382 is capable of providing refresh transactions to
dynamic memories that have internal refresh address
counters. A user can select how often refresh requests
should be made to the Z80Õs External Interface Logic, as
well as the burst size (number of refresh transactions) for
each request iteration. The External Interface Logic grants
these requests by performing refresh transactions with
CAS-before-RAS timing on the /TREFR, /TREFA and
/TREFC bus control signals. In these transactions, /BHEN,
/BLEN and the user specified chip select signal(s) are driv-
en active to facilitate refreshing all the DRAM modules at
the same time. A user can also specify the T1, T2 and T3
waits to be inserted.
Note: The Z382 cannot provide refresh transactions when
it relinquishes the system bus, with its /BREQ input active.
In that situation, the number of missed refresh requests
are accumulated in a counter, and when the Z382 regains
the system bus, the missed refresh transactions will be
performed.
Low Power Standby Mode
The Z382 provides an optional standby mode to minimize
power consumption during system idle time. If this option
is enabled, executing the Sleep instruction stops the
Z382Õs oscillator if it is in use, and in any case stops clock-
ing internal to the Z382 (except to PRT0 if it is enabled)
and at the BUSCLK and IOCLK outputs. The /STNBY and
/HALT signals go Low to indicate that the Z382 is entering
the standby mode. All Z382 operations are suspended, the
bus control signals are driven inactive and the address bus
is driven High. Standby mode can be exited by asserting
any of the /RESET, /NMI, /INT3-/INT0 (if enabled), or op-
tionally, /BREQ inputs.
If standby mode is not enabled, the Sleep instruction does
not stop the Z382Õs oscillator if it is in use, but blocks clock-
ing from internal modules, except PRT0 if it is enabled. In
this case, /STNBY (but not /HALT) goes Low to indicate
the Z382Õs status.
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PRELIMINARY
DS97Z382000