Z80382 Datasheet, PDF (19/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
ASCI Receiver Timing (See Figure 12)
Specifications apply over Standard Operating Conditions unless otherwise noted. C_L = 50 pF for outputs.
Z80382
Z8L382
1
Symbol
Parameter
Min.
Max.
Min.
Max. Units
t79 External Receive Clock Period
50
50
ns
t80 External Receive Clock Low Time
30
30
ns
t81 External Receive Clock High Time
30
30
ns
t82 External Receive Clock Fall Time
5
10
ns
t83 External Receive Clock Rise Time
5
10
ns
t84 RXA Setup to CKA Rise
20
25
ns
t85 RXA Hold from CKA High
5
5
ns
CKA
(input)
RXA
t79
t80
t81
t82
t83
t84
t85
Figure 12. ASCI Receiver Timing
DS97Z382000
PRELIMINARY
19