Z80382 Datasheet, PDF (52/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
SERIAL COMMUNICATION CHANNELS (Continued)
Transmit Shift Register
When the ASCI Transmit Shift Register receives data from
the ASCI Transmit Data Register, the data is shifted out to
the TxA pin. When transmission is completed, the next
byte (if available) is automatically loaded from the TDR into
the TSR and the next transmission starts. If no data is
available for transmission, the TSR idles at a continuous
High level.
Receive Shift Register
When the receiver is enabled, the RXA pin is monitored for
a low. One-half bit time after a low is sensed at RXA, the
ASCI samples RXA again. If it has gone back to High, the
ASCI ignores the previous low and resumes looking for a
new one, but if RXA is still low, it considers this a start bit
and proceeds to clock in the data based upon the internal
baud rate generator or the external clock at the CKA pin.
The number of data bits, parity, multiprocessor and stop
bits are selected by means of control bits in the CNTLA
and CNTLB registers.
After the data has been received, the appropriate MP, par-
ity and one stop bit are checked. Data and any errors are
clocked into the receive data and status FIFOs during the
stop bit if there is an empty position available. Interrupts,
Receive Data Register Full Flag, and DMA requests will
also go active during this time. If there is no space in the
FIFO at the time that the RSR attempts to transfer the re-
ceived data into it, an overrun error occurs.
Receive Data FIFO
When a complete incoming data byte is assembled in the
RSR, it is automatically transferred to the FIFO, which
serves to reduce the incidence of overrun errors. The top
(oldest) character in the FIFO (if any) can be read by
means of the Receive Data Register (RDR).
An overrun occurs if the receive FIFO is still full when the
receiver completes assembly of a character and is ready
to transfer it to the FIFO. If this occurs, the overrun error bit
associated with the previous byte in the FIFO is set. The
latest data byte is not transferred from the shift register to
the FIFO in this case, and is lost. Once an overrun occurs,
the receiver does not place any further data in the FIFO
until the last good byte received has come to the top of the
FIFO and sets the Overrun latch, and software then clears
the Overrun latch.
When a break occurs (defined as a framing error with the
data equal to all zeros), the all-zero byte with its associated
error bits are transferred to the FIFO if it is not full. If the
FIFO is full, an overrun is generated, but the break, fram-
ing error and data are not transferred to the FIFO. Any time
a break is detected, the receiver will not receive any more
data until the RXA pin returns to a high state.
Data transfers from the receive FIFO can be performed us-
ing I/O instructions or by using one of the DMA channels.
This DMA process reads characters from the RDR as an
associated status bit indicates that data is available. The
RxDMA request is disabled when any of the error flags
(PE, FE or OVRN) is set, so that software can identify with
which character a problem is associated.
ASCI Status FIFO/Register
This FIFO contains Parity Error, Framing Error, Rx Over-
run, and Break status bits associated with each character
in the receive data FIFO. The status of the oldest character
(if any) can be read from the ASCI status register, which
also provides several other, non-FIFOed status conditions.
The outputs of the error FIFO go to the set inputs of soft-
ware-accessible error latches in the status register. Writing
a 0 to the Error Flag Reset (EFR) bit in CNTLA is the only
way to clear these latches. In other words, when an error
bit reaches the top of the FIFO, it sets an error latch. If the
FIFO has more data and the software reads the next byte
out of the FIFO, the error latch remains set and does so
until the software writes a 0 to the EFR bit. The error bits
are cumulative, so if additional errors are in the FIFO they
will set any unset error latches as they reach the top.
Baud Rate Generator
The baud rate generator has two modes. The first is the
same as that used in most previous Zilog processors, such
as the Z80180, and provides a dual set of fixed clock divide
ratios. In the second mode, the BRG is configured as a six-
teen-bit down counter that divides the processor clock by
the value in a software accessible, sixteen-bit, time con-
stant register. This allows virtually any frequency to be cre-
ated by appropriately selecting the main processor clock
frequency. The BRG can also be disabled in favor of an ex-
ternal clock on the CKA pin.
The Receiver and Transmitter will subsequently divide the
output of the Baud Rate Generator (or the signal from the
CKA pin) by 1, 16 or 64 under program control.
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PRELIMINARY
DS97Z382000