Z80382 Datasheet, PDF (51/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
TXA0
RXA0
/RTS0
/CTS0
/DCD0
CKA0
Internal Address/Data Bus
ASCI Transmit Data Register
Ch 0: TDR0
ASCI Transmit Shift Register *
Ch 0: TSR0
ASCI Receive Data FIFO
Ch 0: RDR0
ASCI Receive Shift Register *
Ch 0: RSR0
ASCI Control Register A
Ch 0: CNTLA0
ASCI Control Register B
Ch 0: CNTB0
ASCI Status FIFO/Register
Ch 0: STAT0
ASCI Extension Control Reg.
Ch 0: ASEXT0
ASCI DMA Control
Ch 0: ADCR0
ASCI Time Constant High
Ch 0: ASTC0H
ASCI Time Constant Low
Ch 0: ASTC0L
Baud Rate Generator
Channel 0
Interrupt Request
ASCI
Control
ASCI Transmit Data Register
Ch 1: TDR1
ASCI Transmit Shift Register *
Ch 1: TSR1
ASCI Receive Data FIFO
Ch 1: RDR1
ASCI Receive Shift Register *
Ch 1: RSR1
ASCI Control Register A
Ch 1: CNTLA1
ASCI Control Register B
Ch 1: CNTB1
ASCI Status FIFO/Register
Ch 1: STAT1
ASCI Extension Control Reg.
Ch 1: ASEXT1
ASCI DMA Control
Ch 1: ADCR1
ASCI Time Constant High
Ch 1: ASTC1H
ASCI Time Constant Low
Ch 1: ASTC1L
Baud Rate Generator
Channel 1
Note: *Not Program Accessible
1
TXA1
RXA1
/RTS1
/CTS1
/DCD1
CKA1
Figure 30. Asynchronous Serial Communications Interface (ASCI) Block Diagram
DS97Z382000
PRELIMINARY
51