Z80382 Datasheet, PDF (38/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
CENTRAL PROCESSING UNIT (Continued)
tion) and the Rotate Digit instructions. Bytes are operated
on by 8-bit load, arithmetic, logical, and shift and rotate in-
structions. Words are operated on in a similar manner by
the word load, arithmetic, logical, and shift and rotate in-
structions. Block move and search operations can manip-
ulate byte strings and word strings up to 64 KB or words
long. Block I/O instructions have identical capabilities.
Addressing Modes
Addressing modes are used by the 380C to calculate the
effective address of an operand needed for execution of an
instruction. Seven addressing modes are supported by the
CPU. Of these seven, one is an addition to the Z80 CPU
addressing modes (Stack Pointer Relative) and the re-
maining six modes are either existing or extensions to the
Z80 CPU addressing modes.
Register Addressing
The operand is one of the 8-bit registers (A, B, C, D, E, H,
L, IXU, IXL, IYU, IYL, A', B', C', D', E', H' or L'); or is one of
the 16-bit or 32-bit registers (BC, DE, HL, IX, IY, BC', DE',
HL', IX', IY' or SP) or one of the special registers (I or R).
Immediate Addressing
The operand is in the instruction itself and has no effective
address. The DDIR IB and DDIR IW decoder directives al-
low specification of 24-bit and 32-bit immediate operands,
respectively.
Indirect Register Addressing
The contents of a register specify the effective address of
an operand. The HL register is the primary register used
for memory accesses, but BC and DE can also be used.
(For the JP instruction, IX and IY can also be used for in-
direction.) The BC register is used for I/O space accesses.
Direct Addressing
The effective address of the operand is the location whose
address is contained in the instruction. Depending on the
instruction, the operand is either in the I/O or memory ad-
dress space. Sixteen bits of direct address is the norm, but
the DDIR IB and DDIR IW decoder directives allow 24-bit
and 32-bit direct addresses, respectively.
Indexed Addressing
The effective address of the operand is the location com-
puted by adding the two's-complement signed displace-
ment contained in the instruction to the contents of the IX
or IY register. Eight bits of index is the norm, but the DDIR
IB and DDIR IW decoder directives allow 16-bit and 24-bit
indexes, respectively.
Zilog
Program Counter Relative Addressing
An 8-, 16- or 24-bit displacement contained in the instruc-
tion is added to the Program Counter to generate the ef-
fective address. This mode is available only for Jump and
Call instructions.
Stack Pointer Relative Addressing
The effective address of the operand is the location com-
puted by adding the two's-complement signed displace-
ment contained in the instruction to the contents of the
Stack Pointer. Eight bits of index is the norm, but the DDIR
IB and DDIR IW decoder directives allow 16- and 24-bit in-
dexes, respectively.
Instruction Set
The 380C instruction set is an expansion of the Z80 in-
struction set; the enhancements include support for addi-
tional addressing modes and a number of new instruc-
tions.
The 380C is opcode compatible with the Z80 CPU and
Z180 MPU. Thus, a Z80/Z180 program can be executed
on the 380C without modification.
The instruction set is divided into 12 groups by function;
these are listed below. Consult the Z380 UserÕs Manual for
additional details on the instruction set.
Ð 8-bit Load/Exchange
Ð 16/32-bit Load, Exchange, Swap and Push/Pop
Ð Block Transfers and Search
Ð 8-bit Arithmetic and Logical Operations
Ð 16/32-bit Arithmetic Operations
Ð 8-bit Bit Manipulation, Rotate and Shift
Ð 16-bit Rotates and Shifts
Ð Program Control
Ð I/O Operations (Internal)
Ð I/O Operations (External)
Ð CPU Control
Ð Decoder Directives
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PRELIMINARY
DS97Z382000