Z80382 Datasheet, PDF (59/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
MX
Transmitter
First
EOM
Byte
/MX
New
Last
Byte
Byte
1
MR
Receiver
/MR
ACK
ACK
ACK
125 msec
a. General Case
MX
Transmitter
/MX
MR
Receiver
/MR
MX
Transmitter
/MX
MR
Receiver
/MR
New
Byte
EOM
Abort Request
b. Abort Request from the Receiver
First
Byte
2nd
Byte
3rd
Byte
EOM
ACK
First Byte
ACK
ACK
2nd Byte 3rd Byte
c. Maximum Speed Case
Figure 33. Monitor Handshake Timing
Monitor Channel Handling
Before transmitting data on a monitor channel, the proces-
sor should look at the Monitor 0 or 1 active status bit in GCI
Status Register 2 to verify that the channel is inactive. The
processor can then write the data to the Monitor Transmit
Data Register. This will enable the GCI hardware to pro-
ceed with the transmission of this data according to the
monitor channel protocol. On receiving an acknowledge
from the receiver, the transmit data request bit in GCI Sta-
tus Register 1 is set, indicating that the monitor channel is
ready to transmit another byte of data. When the last byte
has been acknowledged by the receiver, the processor
can set the EOM request bit in the GCI Control Register
and the monitor channel will then send an end of message
signal.
On receiving the monitor data, the receiver will write this
data to the monitor receive register and set the appropriate
status bit. This will generate a monitor receive data avail-
able interrupt, instructing the processor to read this data.
Succeeding bytes of data are received in accordance to
the monitor channel protocol and the processor is in-
formed by means of the monitor receive data available in-
terrupt. The processor can force the receiver to ask for an
abort by setting the abort request bit. The receiver will ask
for an abort in transmission by sending an inactive MR for
two consecutive frames. The abort transmission is indicat-
ed in the status bit by the transmitter.
C/I Channel Operation
Data on C/I0 and C/I1 is transmitted continuously in each
frame until new data is to be sent. A change in C/I channel
data is considered valid if it has been received in two con-
secutive frames.
GCI/SCIT Bus Activation and Deactivation
Deactivation, Upstream to Downstream. The upstream
(clock master) unit can initiate deactivation by issuing a se-
ries of software handshakes by means of the C/I0 channel.
Having done so, the upstream unit waits for a deactivation
indication from all downstream (clock slave) units. Once
this is received, a deactivation confirmation is issued, fol-
lowed by stopping the clocks (forcing them Low) and plac-
ing the data pin in a high impedance state. After the clocks
are stopped, the input pin is monitored for the presence of
DS97Z382000
PRELIMINARY
59