Z80382 Datasheet, PDF (64/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC (Continued)
I/O Chip Select Registers
The following I/O-mapped registers are associated with
the I/O chip selects and can be read and written by the
380C processor:
s I/OCS1 High and Low Address Registers
s I/OCS2 High and Low Address Registers
I/O Chip Select 1/2 High and Low Address Registers.
Specify the base address and the I/O block size for I/O
Chip Selects 1 and 2.
RAM AND ROM Chip Selects
Three memory chip select outputs are provided: /ROMCS,
/RAMCSL, and /RAMCSH. They support both 8- and 16-
bit memories, and are asserted for a selected address
range (4 KB to 8 MB) during both memory and I/O cycles.
Unlike Chip Select and /MSIZE signalling, wait state gen-
eration can be specified which occurs only during memory
cycles.
For the selected ROM and/or RAM range, the /MSIZE pin
can be programmed to be forced Low in an open-drain
fashion when the address is in the programmed range,
thus forcing 8-bit accesses in one or both ranges. When
/MSIZE is forced for 8-bit RAM in this way, /RAMCSL is as-
serted for all cycles in the selected address range, and the
/RAMCSH pin assumes its alternate use as port pin PC7.
When /MSIZE is not forced for 8-bit RAM, /RAMCSL is
qualified by /BLEN, and /RAMCSH acts as a chip select
output pin and is qualified by /BHEN.
RAM and ROM Chip Select Registers
The following I/O-mapped registers are associated with
the RAM and ROM chip selects and can be read and writ-
ten by the 380C processor:
s RAM Address High and Low Registers
s ROM Address High and Low Registers
s Memory Mode Register 1
s Memory Mode Register 2
RAM Address High and Low Registers: Specify which
bits of the address bus are used in the address compari-
son and thus, implicitly, the memory block size. This can
range from 4 KB to 8 MB.
ROM Address High and Low Registers: Specify which
bits of the address bus are used in the address compari-
son and thus, implicitly, the memory block size. This can
range from 4 KB to 8 MB.
Memory Mode Register 1. Enables the ROM chip select,
specifies the number of wait states for the ROM chip se-
lect, and specifies the number of T1 wait states for the
RAM chip select.
Memory Mode Register 2. Enables the RAM chip select,
specifies 8- or 16-bit memory accesses for the RAM and
ROM chip selects independently, and specifies the num-
ber of T2 and T3 wait states for the RAM chip select.
Interrupt Logic
The Z382Õs interrupt structure provides compatibility with
the existing Z80 and Z180 with the following exception: the
undefined Opcode trapÕs occurrence is with respect to the
Z380 instruction set, and its response is improved (versus
the Z180) to make trap handling easier. The Z380 offers
additional features to enhance flexibility in system design.
Of the five external interrupt inputs provided, /NMI is a non-
maskable interrupt. The remaining inputs, /INT3-0, are
asynchronous maskable interrupt requests.
In an Interrupt Acknowledge transaction, address outputs
A23-4 are driven to a logic High. One output among A3-0
is driven Low to indicate the maskable interrupt request
being acknowledged. For example, when /INT0 is being
acknowledged, A3-1 are High and A0 is Low.
Interrupt modes 0 through 3 are supported for maskable
interrupt request /INT0, which can be driven by external
and on-chip sources. Modes 0, 1 and 2 have the same
schemes as those in the Z80 and Z180. Mode 3 is similar
to mode 2, except that 16-bit interrupt vectors are expect-
ed from the I/O devices. Note that 8-bit and 16-bit I/O de-
vices can be intermixed in this mode by having external
pull up resistors at the data bus signals D15-8, for exam-
ple.
The external maskable interrupt requests /INT3-1, as well
as the less complex on-chip peripherals (PRTs, ASCIs,
and CSI/O) are handled in an assigned interrupt vectors
mode. INT3-1 can be used as Low or High active level-
sensitive inputs, or as falling or rising edge-triggered in-
puts.
The Z382 can operate in either the Native or Extended
Mode. In Native Mode, PUSHing and POPing of the stack
to save and retrieve interrupted PC values in interrupt han-
dling are done in 16-bit sizes, and the stack pointer rolls
over at the 64-KB boundary. In Extended Mode, the PC
PUSHes and POPs are done in 32-bit sizes, and the stack
pointer rolls over at the 4-GB memory space boundary.
The Z382 provides an Interrupt Register Extension, whose
contents are always output as the address bus signals
A23-16 when fetching the starting addresses of service
routines from memory in interrupt modes 2 and 3 and the
assigned vectors mode. In Native Mode, such fetches are
automatically done in 16-bit sizes and in Extended Mode,
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PRELIMINARY
DS97Z382000