Z80382 Datasheet, PDF (61/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
CSI/O Registers
CSI/O Tx/Rx Data Register. TRDR is used for both CSI/O
The CSI/O channel includes the following I/O-mapped reg- transmission and reception in a half-duplex protocol. Thus,
1 isters that can be read and written by the 380C processor: the system design must ensure that transmit and receive
operations do not occur simultaneously. For example, if a
s Transmit/Receive Data Register
CSI/O transmission is attempted while the CSI/O is receiv-
s CSI/O Control Register
ing data, a CSI/O will not work. Also, the TRDR is not buff-
ered. Thus, attempting to perform a CSI/O transmit while
CSI/O Control Register. CNTR is used to monitor CSI/O
status, enable and disable the CSI/O, enable and disable
interrupt generation, and select the data clock speed and
source.
the previous transmit data is still being shifted out causes
the shift data to be immediately updated, corrupting the
transmit operation in progress. Similarly, reading TRDR
while a transmit or receive is in progress must be avoided.
COUNTERS, TIMERS AND OTHER MISCELLANEOUS LOGIC
Programmable Reload Timer
Timer Reload Reg. High
Ch 0: RLDR0H
Timer Data Reg. High
Ch 0: TMDR0H
Timer Reload Reg. Low
Ch 0: RLDR0L
Timer Data Reg. Low
Ch 0: TMDR0L
Internal Address/Data Bus
Interrupt Request
Timer Control Register
TCR
Timer Prescale Register
TPR
Timer Reload Reg. Low
Ch 1: RLDR1L
Timer Data Reg. Low
Ch 1: TMDR1L
Timer Reload Reg. High
Ch 1: RLDR1H
Timer Data Reg. High
Ch 1: TMDR1H
BUSCLK
Figure 35. Programmable Reload Timer Block Diagram
TOUT
The Z382 contains two separate 16-bit Programmable Re-
load Timers (PRT). Each PRT channel contains a 16-bit
down counter and a 16-bit reload register. The down
counter can be directly read and written and a down
counter overflow interrupt can be programmably enabled
or disabled. Also, PRT1 can be programmed to set the T_OUT
pin High or Low or to toggle it when the channel counts
down to zero. Thus, PRT1 can perform programmable out-
put waveform generation.
The two channels share a common status/control register
and a Timer Prescale Register which allows the time base
for each PRT to be programmed as the Z382 BUSCLK di-
vided by a power of two.
PRT Common Registers
The PRTs share two I/O-mapped registers that can be
read and written by the 380C processor:
s Timer Prescale Register
s Timer Control Register
Timer Prescale Register. Selects the rates at which each
PRT is clocked, providing for BUSCLK divisors ranging
from 1 to 32,768.
Timer Control Register. The TCR monitors the status of
both PRT channels and controls enabling and disabling of
down counting and interrupts. It also controls the effect of
PRT1 on the T_OUT output pin.
PRT Per Channel Registers
The I/O-mapped per-channel registers in each PRT are:
s Timer Data Registers High/Low
s Timer Reload Registers High/Low
Timer Data Registers. Each PRT has a 16-bit Timer Data
Register (TMDR). TMDR is decremented once every clock
output from the timer prescaler, which divides the BUS-
CLK signal of the Z382 by a value which is specified, inde-
pendently for PRT1 and PRT0, in the TPR. When TMDR
DS97Z382000
PRELIMINARY
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