Z80382 Datasheet, PDF (63/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
Watch-Dog Timer
Because of pin multiplexing, ports A and D are available
A Watch-Dog Timer (WDT) with programmable timeout in-
tervals prevents code runaway and possible resulting sys-
tem damage. The /RESET input can be forced as an out-
put upon the terminal count of the WDT, allowing external
peripherals to be reset along with the Z382. Unlike other
only in non-Host applications, and the registers for Ports A
and D are used by the Mimic feature in Host applications.
Additional information on the multiplexing of the Port pins
is provided in the Device Configuration section of this doc-
ument.
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on-chip functions, the WDT is enabled at Reset and must
be disabled by software if its function is not desired. If soft-
ware does not disable the WDT, it must periodically clear
Each port contains two registers accessible in the 380CÕs
I/O address space:
the WDT in order to avoid a hardware reset of the entire
chip. The block diagram of the WDT is shown below (Fig-
ure 41).
s Port Direction Register
s Port Data Register
Internal Address/Data Bus
Bit 3 in the System Configuration Register controls wheth-
er only the lowest eight address lines are decoded, allow-
ing the port data and direction registers to be accessed in
any page of I/O space (as on the Z18x family), or whether
access is limited to a single page (A[15-8] = 0).
WDT Master Register
WDTMR
WDT Command Register
WDTCR
f
Timeout
Generator
WDT Out
Figure 37. WDT Block Diagram
WDT Registers
The CSI/O channel includes the following I/O-mapped reg-
isters that can be read and written by the 380C processor:
s WDT Master Register
s WDT Command Register
Watch-Dog Timer Master Register. This register controls
enabling/disabling of the WDT, its period, and whether the
/RESET pin is driven to reset external devices when the
WDT times out.
WDT Command Register. The WDT decodes two values
written to this register.One value is used to reset the WDT
to a count of zero, the second value must be written to this
register in order to disable the WDT.
Parallel Ports
The Z382 has four 8-bit bidirectional ports called ports A
through D. A Direction Register associated with each port
allows each bit of the port to be programmable as an input
or an output.
Port Direction Register
The Direction Register determines which pins of the port
are inputs and which are outputs.
In Host applications, the Port A and D Direction Registers
are used to buffer data between the HostÕs HD7-0 lines
and the Z382 for the ÒHost DMA MailboxÓ and ÒHost I/O
MailboxÓ functions.
Port Data Register
When the 380C writes to the Data Register of an available
port, the data is stored in this register. Any pins that are
identified as output in the corresponding Port Direction
Register are then driven with the new data. When the
380C reads the Data Register of an available port, the data
on the external pins is returned.
In Host applications, the Port A and D Data Registers are
used for implementation of the ÒHost I/O MailboxÓ feature.
I/O Chip Selects
Two I/O chip selects, /IOCS1 and /IOCS2, are provided to
support I/O access of external peripherals. These chip se-
lects are asserted Low when some number of the 16 LSBs
of the current 380C address match the values pro-
grammed in the IOCS registers.The number of bits actual-
ly compared is specified in one of the registers, providing
I/O decode sizes ranging from 8 to 512 bytes.
Address comparisons take place during both memory and
I/O cycles. The I/O Chip Selects are not asserted in IN-
TACK cycles.
DS97Z382000
PRELIMINARY
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