Z80382 Datasheet, PDF (29/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
Table 4. MPU Signals
Pin
Pin Name Number(s)
Description
1
A23 - 0
141 - 144, Address Bus (outputs, active High, tri-state): These non-multiplexed address signals pro-
1 - 4, 6 - 13, vide a linear memory address space of 16 MB. The address signals are also used to ac-
15 - 22 cess I/O devices.
/BUSACK
132 Bus Acknowledge (output, active Low, tri-state): This signal, when asserted, indicates
that the 380C has accepted an external bus request and has tri-stated its output drivers for
the address bus, databus and the bus control signals /TREFR, /TREFA, /TREFC, /BHEN,
/BLEN, /MRD, /MWR, /IORQ, /IORD, and /IOWR.
/BHEN
/BLEN
The 380C cannot provide any DRAM refresh transactions while it is in the bus acknowl-
edge state.
118 Byte High Enable (output, active Low, tri-state): This signal is asserted at the beginning
of a memory or refresh transaction, to request an operation on D15-8. If software initiates
a 16-bit memory operation, but /MSIZE is asserted indicating a byte-wide memory, only
the data on D7-0 is transferred in the current transaction, and another transaction is per-
formed to transfer the other data byte, also on D7-0.
119 Byte Low Enable (output, active Low, tri-state): This signal is asserted at the beginning of
a memory or refresh transaction, to request an operation on D7-0. If software initiates a
16-bit memory transaction, but /MSIZE is asserted indicating a byte-wide memory, only the
data on D7-0 is transferred in the current transaction, and another transaction is performed
to transfer the other data byte, also on D7-0.
/BUSREQ
BUSCLK
D15-0
133
127
24 - 31
33 - 40
To align Z382 documentation and terminology with historical Z80 and industry (e.g., Intel)
practice, the names of the /BHEN and /BLEN pins, as well as the D15-8 and D7-0 pins,
have been swapped on the Z382 compared to the Z380. This fact should be significant
only for those using a Z380 Emulator in a Z382-based project.
Bus Request (input, active Low): When this signal is asserted, an external bus master is
requesting control of the bus. /BREQ has higher priority than all nonmaskable and
maskable interrupt requests.
Bus Clock (output, active High, tri-state): This signal is the reference edge for the majority
of other signals generated by the 380C. Its frequency may be that of the CLKI pin, or CLKI
divided by two or times two.
D15-0 Data Bus (input/output, active High, tri-state): This bidirectional 16-bit data bus is
used for data transfer between the 380C and memory or I/O devices. In a memory word
transfer, the even-addressed (A0=0) byte is transferred on D7-0, and the odd-addressed
(A0=1) byte on D15-8. 8-bit memories should be connected to D7-0, while 8-bit I/O devices
should be attached to D15-8 (this difference tends to equalize electrical loading).
/HALT
/STNBY
/INT3
/INT2
/INT1
/INT0
(See note under /BLEN pin description.)
121 HALT, STANDBY Status (outputs, active Low): These two outputs indicate the status of
120 the Z382 as follows:
/STNBY
H
H
L
L
/HALT
H
L
H
L
Mode
Normal instruction execution
HALT instruction
SLEEP Mode: clock runs but is blocked from most of the chip
STANDBY Mode: oscillator is stopped
139 Interrupt Requests (inputs): Asynchronous maskable interrupt inputs. Can be selected as
138 low- or high-level sensitive, or as falling- or rising-edge triggered.
137
136 Interrupt Request (input, active Low): /INT0 is logically ORed (positive-logic ANDed) with
the interrupt requests from the on-chip Mimic, DMAs, and HDLC controllers, to create the
processorÕs /INT0 input.
DS97Z382000
PRELIMINARY
29