Z80382 Datasheet, PDF (48/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
DMA CHANNELS (Continued)
On fetching any Type/Status value except Transfer in List
or Ready Buffer, the DMA channel clears its Run bit and
requests an interrupt if its List Interrupt Enable bit is 1. This
checking of the Type/Status byte helps prevent disorderly
operation as well as buffer-ring wraparound.
On fetching a Transfer in List entry, the DMA channel
fetches the Address portion of the entry, loads it into its
LAR, and proceeds to fetch another list entry from that ad-
dress. This is the mechanism by which buffer rings and
linked lists are constructed.
If software needs to know when a certain amount of data
has been sent or received, such as an Address field in a
received HDLC frame, it can set up a buffer of that length
with its own list entry. The DMA channel can provide an in-
terrupt at the end of the buffer if desired.
When a DMA channel fetches a Type/Status byte from
memory, it asserts the Type Fetch signal to its client de-
vice. This prompts the client device to capture the Com-
mand if bits D7-6 of the Type/Status byte are 01 or 10.
For example, the HDLC Transmitter uses the three LS bits
of such a Type/Status byte to indicate how many bits to
send from the last byte of the frame. The HDLC Receiver
doesnÕt use any Command bits, so that Ready Buffer
codes, with and without Command, are equivalent for
HDLC reception.
Upon fetching any Ready Buffer entry, the DMA channel
rewrites the Type/Status byte to the ÒBuffer in ProgressÓ
code, and then fetches the Address and Buffer Length
fields and loads them into its Buffer Address and Length
Registers (BAR and BLR) respectively. Thereafter the
DMA channel transfers data into or out of the buffer, under
control of the Data Request line from its client device. If
there is no request at this point, as would typically be the
case when software starts a ÒreceiveÓ channel, the DMA
channel relinquishes bus control to the processor or anoth-
er DMA channel, and goes idle until the device asserts
Data Request and/or Terminate. For Type/Status bytes re-
questing ÒNotify device at end of bufferÓ, the DMA channel
will assert its clientÕs End of Buffer line at the appropriate
time.
Zilog
Once a DMA channel has been started and has fetched its
first list entry, it does nothing further unless and until its cli-
ent device asserts Data Request and/or Terminate. When
the client devices does so, the DMA channel requests bus
access from the processor. When access is granted, or
when it is continuing operation after fetching a list entry,
the DMA channel proceeds as follows:
If the device is asserting Data Request, with or without Ter-
minate:
a. The DMA channel asserts Data Acknowledge to the
device.
b. If its BLR indicates the buffer is ending, and the Sta-
tus/Type byte for this buffer said ÒNotify DeviceÓ, the
DMA channel also asserts the End of Buffer signal.
c. At the same time, the DMA channel places the ad-
dress in its BAR on the address bus, and sets the con-
trol signals for a memory read or write per the I/O bit in
its DMA Control/Status Register (DCSR).
d. Depending on the data direction, Data Acknowledge
makes the device either provide a byte of data on the
data bus, or capture a byte of data from the data bus.
How (and whether) a client device uses ÒEnd of BufferÓ is
device-dependent. The HDLC Transmitter passes this in-
dication through its TxFIFO, and terminates the Tx frame
after sending the data with which the DMA channel assert-
ed End of Buffer. (Because of this facility, the only time that
an ÒunderrunÓ may occur at the HDLC Transmitter is when
the DMA doesnÕt provide data fast enough, INSIDE a
frame.)
The HDLC Receiver doesnÕt do anything with ÒEnd of Buff-
er,Ó so Ready Buffer codes with or without ÒEOBÓ are
equivalent for HDLC receiving.
At the end of each data transfer, the DMA channel incre-
ments the BAR by 1 and decrements the BLR by 1.
If the device signalled Data Request but not Terminate,
and the Buffer Length Register has not been counted
down to zero, and the Burst bit in the channelÕs DCSR is
set, the DMA channel checks Data Request again. If Burst
is 0, and/or if the device negates Data Request, the chan-
nel gives the bus back to the processor or another DMA
channel, else it goes back to do another data transfer.
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PRELIMINARY
DS97Z382000