Z80382 Datasheet, PDF (33/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
Table 7. Parallel Ports
Pin
Pin Name Number(s)
Description
1
PA7-0
78 - 85 Parallel Ports A, B, C, D (Input/Outputs): These lines can be configured as inputs or out-
PB7-0
51 - 58 puts on a bit-by-bit basis. In an ISA or PCMCIA application, Ports A and D are not pinned
PC7-0
44 - 45, out, the registers for Ports A and D are used by the Mimic function, and Ports B and C are
47 - 49, 109, selectively multiplexed with the on-chip peripherals (ASCIs, CSI/O, PRT). In other applica-
101, 97 tions all four ports are available with minimal multiplexing.
PD7-0
69 - 76
Pin Name
TxD0
TxD1
TxD2
RxD0
RxD1
RxD2
TxC0/FSC0
TxC1/FSC1
TxC2/FSC2
RxC0/BCL0
RxC1/BCL1
RxC2/BCL2
/TxEN0
/TxEN1
/TxEN2
DU
DD
DCL
FSC
Table 8. HDLC Serial Channel and GCI/SCIT Signals
Pin
Number(s)
Description
98
HDLC Transmit (outputs): These pins are used to transmit serial data from the HDLC con-
102 trollers when they are not operating by means of the GCI/SCIT interface.
107
99
HDLC Receive (inputs): These pins are used to receive serial data for the HDLC control-
103 lers when they are not operating by means of the GCI/SCIT interface.
108
96
HDLC Transmit Clock/Frame Sync(input/outputs): In non-TDM, non-GCI modes, these
100 can be used as external bit clock inputs or can be programmed to output the Tx clock. In
105 non-GCI TDM mode, these pins carry the Frame Sync pulse.
97
HDLC Clock/Bit Clock (inputs): Optional external bit clock inputs.
101
106
93
HDLC Transmit Enable (outputs, active Low): In a non-GCI TDM mode, these outputs in-
94
dicate when an HDLC Transmitter is enabled and is in its active time slot. In non-GCI, non-
109 TDM mode, these outputs are Low when the Transmitter is enabled. They can be used to
enable an external driver on the TxD line.
105 GCI/SCIT Data Upstream, Downstream (input/outputs, open-drain): The two bidirection-
107 al data streams of the GCI/SCIT interface.
106 GCI/SCIT Clock (input): Bit clock for the GCI/SCIT interface.
108 GCI/SCIT Frame Sync (input): This pin is used to synchronize the GCI/SCIT serial frames.
This pin is driven active by Òthe upstream deviceÓ (ISDN transceiver) at the start of each
GCI/SCIT frame.
DS97Z382000
PRELIMINARY
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