Z80382 Datasheet, PDF (45/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
PCMCIA
Interface Control
Z80382/Z8L382
High-Performance Data Communications Processors
Internal Address/Data/Control Bus
1
Attribute Memory
(see Figure 32 below)
Configuration
Registers
I/O Address
Decoder
Mimic Chip
Select
Host PCMCIA Address/Data/Control Bus
Figure 27. PCMCIA Interface
PCMCIA I/O Interface Control
The I/O interface contains the main functionality of the PC-
MCIA block. The interface decodes addesses for I/O ac-
cesses by the Host according to the PCMCIA standard.
The Host writes to the Configuration Option Register an in-
dex to select the base address of the desired I/O address
range. After configuration, I/O accesses to this address
range are recognized, and the Mimic chip select is assert-
ed when a valid I/O access is performed and the address
is in the configured address range.
Attribute Memory
The attribute memory is the primary mechanism for trans-
fers of configuration data and status between the host sys-
tem and the PCMCIA card. As shown in Figure 32, the at-
tribute memory is segmented into several sections. The
Card Information section is 240 bytes of RAM which is
loaded by the 380C with information describing the card
and its resource requirements, data needed by the Host to
configure the card. A portion of the attribute memory al-
lows the host to access the I/O Mailbox registers. Lastly,
sections in the attribute memory space are assigned to the
Configuration Registers and the Base Address Registers.
On the Host side, attribute memory is accessible only on
even byte addresses. On the 380C side it can be accessed
as bytes or words.
0206
0200
01FE
I/O Mailbox
01FF
Card Information (RAM)
0110
0188
010E
0187
ConÞguration Registers
0100
0180
00FE
017F
Base Address Registers
00F0
00EE
0178
0177
Card Information (RAM)
0000
0100
Figure 28. PCMCIA Attribute Memory Organization
DS97Z382000
PRELIMINARY
45