Z80382 Datasheet, PDF (72/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
HDLC REGISTERS
Register Name
HDLC Vector Register
HDLC0 Transmit Mode Register
HDLC0 Transmit Interrupt Register
HDLC0 Transmit Control/Status
HDLC0 Transmit Fill Register
HDLC0 Receive Mode Register
HDLC0 Receive Interrupt Register
HDLC0 Counter Access Port
HDLC0 DMA Select Register
HDLC1 Transmit Mode Register
HDLC1 Transmit Interrupt Register
HDLC1 Transmit Control/Status Register
HDLC1 Transmit Fill Register
HDLC1 Receive Mode Register
HDLC1 Receive Interrupt Register
HDLC1 Counter Access Port
HDLC1 DMA Select Register
HDLC2 Transmit Mode Register
HDLC2 Transmit Interrupt Register
HDLC2 Transmit Control/Status Register
HDLC2 Transmit Fill Register
HDLC2 Receive Mode Register
HDLC2 Receive Interrupt Register
HDLC2 Counter Access Port
HDLC2 DMA Select Register
GCI/SCIT REGISTERS
Register Name
GCI Control Register
GCI Status Register 1
GCI Status Register 2
GCI Interrupt Enable Register
MON0 Transmit Data Register
MON0 Receive Data Register
MON1 Transmit Data Register
MON1 Receive Data Register
C/I0 Transmit Data Register
C/I0 Receive Data Register
C/I1 Transmit Data Register
C/I1 Receive Data Register
I/O Address
%003D
%0060
%0061
%0062
%0063
%0064
%0065
%0066
%0067
&0068
%0069
%006A
%006B
%006C
%006D
%006E
%006F
%0070
%0071
%0072
%0073
%0074
%0075
%0076
%0077
Zilog
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I/O Address
%00C0
%00C1
%00C2
%00C3
%00C4
%00C4
%00C5
%00C5
%00C6
%00C6
%00C7
%00C7
Access
R/W
RO
R/W
R/W
WO
RO
WO
RO
WO
RO
WO
RO
72
PRELIMINARY
DS97Z382000