Z80382 Datasheet, PDF (36/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
CENTRAL PROCESSING UNIT (Continued)
because of the possibility of "misplacing" interrupt service
routines or vector tables during the translation from Ex-
tended mode back to Native mode.
In addition to Native and Extended mode, which is specific
to memory space addressing, the 380C can operate in ei-
ther Word or Long Word mode specific to data load and ex-
change operations. In Word mode (the reset configura-
tion), all word load and exchange operations manipulate
16-bit quantities. For example, only the low-order words of
the source and destination are exchanged in an exchange
operation, with the high-order words unaffected.
In Long Word mode, all 32 bits of the source and destina-
tion are exchanged. The 380C implements two instruc-
tions plus decoder directives to allow switching between
Word and Long Word modes. The two instructions perform
a global switch, while the decoder directives select a par-
ticular mode only for the instruction that they precede.
Note that all word data arithmetic (as opposed to address
manipulation arithmetic), rotate, shift and logical opera-
tions are always in 16-bit quantities. They are not con-
trolled by either the Native/Extended or Word/Long Word
selections. The exceptions to the 16-bit quantities are, of
course, those multiply and divide operations with 32-bit
products or dividends.
Lastly, all word input/output operations are performed on
16-bit values.
CPU Address Spaces
The 380C architecture supports five distinct address spac-
es corresponding to the different types of locations that
can be accessed by the CPU. These five address spaces
are: CPU register space, CPU control register space,
memory address space, and I/O address space (on-chip
and external).
CPU Register Space
The CPU register space is shown in Figure 26 and con-
sists of all of the registers in the CPU register file. These
CPU registers are used for data and address manipula-
tion, and are an extension of the Z80 CPU register set, with
four sets of this extended Z80 CPU register set present in
the 380C. Access to these registers is specified in the in-
struction, with the active register set selected by bits in the
Select Register (SR) in the CPU control register space.
Primary and Working Registers. The working register
set is divided into the two register files; the primary file and
the alternate file (designated by Ô). Each file contains an 8-
bit Accumulator (A), a Flag register (F), and six general-
purpose registers (B, C, D, E, H, and L). Only one file can
be active at any given time, although data in the inactive
file can still be accessed. Exchange instructions allow the
Zilog
programmer to exchange the active file with the inactive
file.
The accumulator is the destination register for 8-bit arith-
metic and logical operations. The six general-purpose reg-
isters can be paired (BC, DE, and HL), and are extended
to 32 bits by the ÔzÕ extension to the register to form three
32-bit general-purpose registers. The HL register serves
as the 16-bit or 32-bit accumulator for word operations.
CPU Flag Register. The Flag register contains six flags
that are set or reset by various CPU operations:
Ð Carry
Ð Add/Subtract
Ð Parity/Overßow
Ð Half Carry
Ð Zero
Ð Sign
Index Registers. The four Index registers, IX, IXÕ, IY and
IYÕ, each hold a 32-bit base address that is used in the In-
dexed addressing mode. The Index registers can also
function as general-purpose registers with the upper and
lower bytes of the lower 16 bits being accessed individual-
ly.
Interrupt Register. The Interrupt register (I) is used in in-
terrupt modes 2 and 3 for /INT0 to generate a 32-bit indi-
rect address to an interrupt service routine. The I register
supplies the upper 24 or 16 bits of the indirect address and
the interrupting peripheral supplies the lower 8 or 16 bits.
In the Assigned Vectors mode for /INT1-3, the upper 16
bits of the vector are supplied by the I register; bits 15-9
are the assigned vector base and bits 8-0 are the assigned
vector unique to each of /INT1-3.
Program Counter. The Program Counter (PC) is used to
sequence through instructions in the currently executing
program and to generate relative addresses. The PC con-
tains the 32-bit address of the current instruction being
fetched from memory. In the Native mode, the PC is effec-
tively only 16 bits long, as carries from bit 15 to bit 16 are
inhibited in this mode. In Extended mode, the PC is al-
lowed to increment across all 32 bits.
R Register. The R register can be used as a general-pur-
pose 8-bit read/write register.
36
PRELIMINARY
DS97Z382000