Z80382 Datasheet, PDF (50/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
DMA CHANNELS (Continued)
DMA Control/Status Register
Controls items such as I/O Direction, enabling/disabling
Burst Mode, and enabling and disabling interrupts. Also
provides certain per channel DMA and interrupt status
conditions.
Centralized DMA Registers
Two registers provide overall control and status of the
DMA subsystem:
s DMA Control Register
s DMA Vector Register
(DMACR)
(DMAVR)
DMA Control Register (DMACR)
This register controls when bus control is returned to the
380C processor after a DMA channel has operated. It also
provides modes whereby the Buffer Address and Buffer
Length per-channel registers can be read and written.
DMA Vector Register (DMAVR
This register contains the base interrupt vector for the
DMA channels. It also identifies, during an interrupt ac-
knowledge cycle, the interrupting DMA Channel.
SERIAL COMMUNICATION CHANNELS
The Z382 provides several means of serial data communi-
cations. These are the Asynchronous Serial Communica-
tion Interface (ASCI), the HDLC controllers, the GCI/SCIT
interface and the Clocked Serial I/O Channel.
Asynchronous Serial Communications Inter-
face (ASCI)
The Z382 provides two independently programmable AS-
CIs (UARTs), each including a flexible baud rate genera-
tor. Key features of the ASCIs include:
s Full-duplex operation
s Programmable data format
Ð 7- or 8- data bits with optional ninth bit for
multiprocessor communication
Ð One or two stop bits
Ð Odd, even or no parity
s Programmable baud rate generator
Ð Divide-by-one, divide-by-16 and divide-by-64
modes
s Up to three modem control signals per channel,
depending on operating mode of the Z382
s Programmable interrupt conditions
s Four level data/status FIFOs for the receivers
s Receive parity, framing and overrun error detection
s Optional operation with on-chip DMA controllers
Figure 34 below illustrates the major functional blocks
within the ASCI.
Transmit Data Register
Data written to the ASCI Transmit Data Register (TDR) is
transferred to the Transmit Shift Register (TSR) as soon as
the TSR is empty. Data can be written while the TSR is
shifting out the previous byte of data, providing double
buffering for the transmit data.
Data transfers into the TDR can be performed using I/O in-
structions or by using one of the DMA channels. This DMA
process loads characters into the TDR as an associated
status bit indicates that it has become available for data.
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PRELIMINARY
DS97Z382000