Z80382 Datasheet, PDF (73/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382 MIMIC REGISTERS
Register Name
MMC Mimic Master Control Register
IUS/IP Interrupt Pending
IE Interrupt Enable
IVEC Interrupt Vector
RTCR Receive Time Constant
TTCR Transmit Time Constant
DLM Divisor Latch (MSByte)
DLL Divisor Latch (LSByte)
SCR Scratch Register
MSR Modem Status Register
LSR Line Status Register
MCR Modem Control Register
LCR Line Control Register
IER Interrupt Enable Register
RBR Receiver Buffer Register
THR Transmitter Holding Register
Mimic DMA Control Register
FSCR FIFO Status and Control Register
TTTC Transmitter Timeout Time Constant Register
RTTC Receiver Timeout Time Constant Register
IIR Interrupt IdentiÞcation Register
FCR FIFO Control Register
Mimic ModiÞcation Register
Host DMA Control Register
Mimic BRG High Constant Register
Mimic BRG Low Constant Register
IOBRG Register
Host I/O Status Register
Host DMA Mailbox Control Register
Host DMA Transmit Register 1
Host DMA Receive Register 1
Host DMA Transmit Register 0
Host DMA Receive Register 0
Z80382/Z8L382
High-Performance Data Communications Processors
I/O Address
%00FF
%00FE
%00FD
%00FC
%00FB
%00FA
%00F9
%00F8
%00F7
%00F6
%00F5
%00F4
%00F3
%00F1
%00F0
%00F0
%00EF
%00EC
%00EB
%00EA
None
%00E9
%00E9
%00e6
%00E1
%00E0
%00D6
%00D5
%00D2
%00D1
%00D1
%00D0
%00D0
Access
R/W
Host
1
None
R/Wb7
None
R/W
None
R/W
None
R/W
None
R/W
None
RO
%01, DLAB=1, R/W
RO
%00, DLAB=1, R/W
RO
%07, R/W
R/Wb7-4
%06, RO
R/Wb6432
%05, RO
RO
%04, R/W
RO
%03, R/W
RO
%01, DLAB=0, R/W
WO
%00, DLAB=0, RO
RO
%00, DLAB=0, WO
R/W
None
R/W7-4
None
R/W
None
R/W
None
None
%02, RO
RO
%02, RO
WO
None
R/W
None
R/W
R/W
R/W
W bit1/R
Base + 10b R
R/W
None
RO
/HDAK1, /HWR lo (Note)
WO
/HDAK1, /HRD lo
RO
/HDAK0, /HWR lo
WO
/HDAK0, /HRD lo
DS97Z382000
PRELIMINARY
73