Z80382 Datasheet, PDF (10/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
AC CHARACTERISTICS
380C Processor Timing (See Figure 4)
Specifications apply over Standard Operating Conditions unless otherwise noted. C_L = 50 pF for outputs.
Z80382
Z8L382
Symbol
Parameter
Min.
Max.
Min.
Max. Notes Unit
t1 Clock Cycle Time
t2 Clock High Time
t3 Clock Low Time
t4 Clock Rise Time
t5 Clock Fall Time
t6 CLKI Low to BUSCLK High Delay
t7 CLKI High to BUSCLK Low Delay
t8 BUSCLK High to Output Valid
t9 BUSCLK Low to Output Valid
t10 Input Setup to BUSCLK Rise
t11 Input Hold from BUSCLK High
t12 /BUSREQ Setup to BUSCLK Fall
t13 /BUSREQ Hold from BUSCLK Low
t14 /WAIT Setup to BUSCLK Rise
t15 /WAIT Hold from BUSCLK High
t16 /WAIT Setup to BUSCLK Fall
t17 /WAIT Hold from BUSCLK Low
t18 /NMI Width Low
t19 /RESET Width Low
t20 /INT1, /INT2, /INT3 Low Width
t21 /INT1, /INT2, /INT3 High Width
25
DC
50
DC
1
ns
10
20
1
ns
10
20
1
ns
3
5
1
ns
3
5
1
ns
25
35
ns
25
35
ns
10
10
2
ns
10
10
3
ns
10
15
4
ns
0
0
4
ns
10
15
5
ns
0
0
5
ns
10
15
6
ns
0
0
6
ns
15
15
6
ns
0
0
6
ns
15
15
ns
10
10
t1
15
15
7
ns
15
15
7
ns
Notes:
1. Applies to the oscillator or external clock input. The maximum internal clock frequency (BUSCLK) is limited to 20 MHz for the
Z80382 and 10 MHz for the Z8L382. Input clock frequencies greater than these values must use the CLKI/2 mode for creating
BUSCLK. This is the default state after Reset.
2. Applies to A23-0, /BHEN, /BLEN, IOCLK, /IOCS1, /IOCS2, /ROMCS, /RAMCSL, /RAMCSH, /M1, /BUSACK, /MRD, /MWR, /TRE-
FA, /TREFC, /TREFR
3. Applies to D15-0, /HALT, /STNBY, /IORQ, /IORD, /IOWR, /MSIZE, /BUSACK, /MRD, /MWR, /TREFC, /TREFR
4. Applicable for Data Bus and /MSIZE inputs.
5. /BUSREQ can also be asserted/deasserted asynchronously.
6. External waits asserted at /WAIT input.
7. In edge-triggered mode.
10
PRELIMINARY
DS97Z382000