Z80382 Datasheet, PDF (67/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
Peripheral Function Control Registers
Refresh Register 2. Enables the refresh function and de-
The functions described above are controlled by a number fines the number of refresh transactions per refresh re-
of I/O mapped on-chip registers:
s Clock Control Register
s I/O Waits Register
quest made to the Z382Õs External Interface Logic.
1
Refresh Wait Register. Defines the number of T1, T2 and
T3 wait states to be inserted in refresh transactions.
s Refresh Registers 0, 1 and 2
s Refresh Wait Register
Standby Mode Control Register. Enables the Z382 to go
into low-power standby mode when the Sleep instruction is
s Standby Mode Control Register
Clock Control Register. Controls how BUSCLK is de-
rived from the input clock (CLKI, CLKI/2 or CLKI x 2), pro-
vides a means of disabling CLKO to save power and re-
duce noise if an external clock is used, and controls the I/O
Clock Rate (BUSCLK/8 to BUSCLK).
executed, allows asserting /BREQ to exit the mode, and
specifies the approximate running duration of a warm-up
counter that provides a delay before the Z382 resumes its
clocking and operations, from the time an interrupt or bus
request (if so enabled) is asserted to exit standby mode.
Device Configuration
I/O Waits Register. Allows for up to seven wait states to
be inserted in external I/O read and write transactions, and
at the latter portions of interrupt transactions to capture in-
terrupt vectors. Also allows for up to seven wait states to
In addition to the configuration options provided in the reg-
isters associated with each of the major functional blocks
in the Z382, there are two registers which control the over-
all device configuration:
be inserted at the early portions of interrupt acknowledge
transactions, for the interrupt daisy chain through on-chip
and possibly external I/O devices to settle.
s System Configuration Register
s Pin Multiplexing Register
Refresh Register 0. Defines the interval between refresh
requests to the Z382Õs External Interface Logic.
Refresh Register 1. Provides the Missed Requests
Count. This count increments by one when a refresh re-
quest is made and decrements by one when the Z382Õs
External Interface Logic completes each burst of refresh
transactions. A user can read the count status, and if nec-
essary, take corrective actions such as adjusting the burst
size.
DS97Z382000
PRELIMINARY
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