Z80382 Datasheet, PDF(42/77 Page) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

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Z80382 Datasheet, PDF (42/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

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Z80382/Z8L382

High-Performance Data Communications Processors

Zilog

HOST INTERFACE (Continued)

Mimic-Host Interface Registers

In addition to the Mimic programming registers, the Z382

contains a register set for interfacing with the Host by

means of the Mimic. These registers are used to emulate

the 16550 UART so that the Host can access these regis-

ters just as if it was interfacing with the UART. This pro-

vides software compatibility with existing Host communi-

cation software. The registers are:

Host 380C I/O

Address1 Address

Receiver Buffer Register

Transmit Holding Register

Interrupt Enable Register

Interrupt ID Register

Line Control Register

Modem Control Register

Line Status Register

Modem Status Register

Scratch Register

Divisor Latch MS Byte

Divisor Latch LS Byte

FIFO Control Register

Mimic ModiÃcation Reg.

%002

%012

%02

%03

%04

%05

%06

%07

%013

%003

%02

%00F0

%00F1

%00F3

%00F4

%00F5

%00F6

%00F7

%00F9

%00F8

%00E9

Note:

1. The host address is relative to the Mimic base address d

coded by the PnP ISA or PCMCIA modules in the Z382.

2. DLAB (LCR[7]) = 0.

3. DLAB (LCR[7]) = 1.

Baud Rate Generator

The Baud Rate Generator (BRG) provides emulation tim-

ing for the Mimic. The BRG output clocks the Mimic emu-

lation counter, while the BRG itself is clocked by the BUS-

CLK output of the 380C. Two 8-bit registers are provided

to program the BRG time constant. Design is such that on-

the-fly modification of the registers does not cause irregu-

lar BRG output.

Host DMA Mailbox

The Host DMA Mailbox facility provides a path for Host

DMA data transfers separate from the Mimic COM port.

Commands and data flow over the COM port, while the

DMA path can be used for other purposes. The Host DMA

Mailbox feature includes control registers that allow Host

DMA data transfer between Host memory and, for exam-

ple, a modem speaker/microphone codec. Transfers are

driven by the HostÃs DMA on one side; Z382 DMA chan-

nel(s) or programmed I/O can be used on the other side.

Thus, several modes of operation can be programmed:

Ã Host DMA Write, Z382 Polled Input

Ã Host DMA Read, Z382 Polled Output

Ã Host DMA Write with Z382 DMA

Ã Host DMA Read with Z382 DMA

On the ISA bus, the Z382 can use two independent DMA

Mailbox facilities. When either of these facilities is enabled

in the Plug and Play module, that module signals a DMA

request by driving HDREQ0 or HDREQ1 High; if a facility

is disabled, the corresponding HDREQ pin is tri-stated. A

Low on one of the Acknowledge signals, /HDACK0 or

/HDACK1, more or less simultaneously with /HWR or

/HRD Low when the corresponding HDREQ line is being

driven High, indicates a DMA cycle.

In a PCMCIA socket, only one DMA Mailbox can be used.

When an option bit in one of the PCMCIA registers is 1, a

DMA request is signalled by setting the /INPACK output

low. A DMA cycle is signalled by having the /PCREG line

High while /PCIORD or /PCIOWR goes Low.

Plug and Play Interface

This module, with support from appropriate Z382-based

firmware, complies with version 1.0a of the MicrosoftÂª /In-

telÂª ÃPlug and Play ISAÃ specification.

The Z382Ãs PnP module provides for I/O address decod-

ing, interrupt channel selection and DMA channel selec-

tion. Pin limitations constrain the internal address decod-

ing for I/O addresses to 12 bits. Since 16-bit decoding is

preferred for full Plug and Play compliance, an additional

input, HAEN, is provided which must be Low for a valid ad-

dress decode. This permits external decoding of HA15-12.

PRELIMINARY

DS97Z382000

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