Z80382 Datasheet, PDF (65/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
in 32-bit sizes. These starting addresses should be even- quest being recognized as A8-0. The assigned vectors are
aligned in memory locations. That is, their least significant as follows:
bytes should have addresses with A0 = 0.
Interrupt Priority Ranking
The Z382 assigns a fixed priority ranking to handle its ma-
jor categories of interrupt sources, as follows:
Interrupt Source
/INT1
/INT2
Assigned Interrupt
1
Vector
00H
04H
Priority
Highest
Interrupt Sources
Trap (undeÞned opcode)
/NMI
/INT0 (includes DMAs, Mimic,
HDLC controllers)
/INT1
/INT2
GCI/SCIT
PRT0
PRT1
Reserved
GCI/SCIT
PRT0
PRT1
CSI/O
ASCI0
ASCI1
Plug and Play or PCMCIA
I/O Mailbox
/INT3
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
CSI/O
ASCI0
ASCI1
Trap Interrupt
The 380C generates a trap when an undefined opcode is
encountered. The trap is enabled immediately after reset,
Lowest
Plug and Play ISA or PCMCIA
I/O Mailbox
/INT3
and it is not maskable. This feature can be used to in-
crease software reliability or to implement extended in-
structions. An undefined opcode can be fetched from the
instruction stream, or it can be returned as a vector in an
INT0 Peripherals
interrupt acknowledge transaction in interrupt mode 0.
Those on-chip peripherals capable of generating their own
interrupt vectors, including the Mimic, DMAs, and HDLC
controllers, have their interrupt requests logically ORÕed
with the external /INT0 pin to produce the INT0 signal pre-
sented to the 380C processor. These interrupt sources are
consecutive in the INT0 daisy-chain, but their relative pri-
ority can be programmed in the System Configuration
Register. Their priority relative to external INT0 sources is
controlled by how the Z382Õs IEI and IEO pins are connect-
Nonmaskable Interrupt
The nonmaskable interrupt input /NMI is edge sensitive,
with the 380C internally latching the occurrence of its fall-
ing edge. When the latched version of /NMI is recognized,
the interrupted PC (Program Counter) value is pushed
onto the stack, certain status flag manipulations are per-
formed, and the 380C commences to fetch and execute in-
structions from address 00000066H.
ed.
RETI Instruction
Assigned Interrupt Vectors Mode (INT1-3, PRTs,
CSI/O, ASCIs)
When the Z382 recognizes /INT1-3, or a request from an
on-chip peripheral that cannot supply an interrupt vector (a
PRT, CSI/O, or ASCI), it generates an Interrupt Acknowl-
edge transaction which is different from that for /INT0. This
Interrupt Acknowledge transaction has /IORQ active for
external monitoring purposes, but /M1, /IORD, and /IOWR
inactive so as not to stimulate external devices. The inter-
The original Z80 family I/O devices (PIO, SIO, CTC) are
designed to monitor the Return from Interrupt Opcodes in
the instruction stream, signifying the end of the current in-
terrupt service routine. On the Z382, the M1 signal is active
during all instruction fetch transactions. Since the Z382
may not execute an RETI that it fetches, and because it
supports a 16-bit data bus, only half of which is visible to
an 8-bit peripheral, the Z382 does not support RETI de-
coding by the PIO, SIO, and CTC.
rupted PC value is PUSHed onto the stack. IEF1 and IEF2
are cleared, disabling further maskable interrupt requests.
The starting address of an interrupt service routine is
fetched from a table entry and loaded into the PC to re-
sume execution. The address of the table entry is com-
posed of the I Extend contents as A31-16, the seven Vec-
tor Base bits of the Assigned Vectors Base Register as
A15-9 and an assigned interrupt vector specific to the re-
DS97Z382000
PRELIMINARY
65