Z80382 Datasheet, PDF (54/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
SERIAL COMMUNICATION CHANNELS (Continued)
Zilog
Internal Address/Data Bus
Transmit DMA Controller
DMA #x
Receive DMA Controller
DMA #y
TXD0
Transmit FIFO *
Ch 0
Transmit Shift Register *
Ch 0
Transmitter
State Machine
Transmit Mode Register
Ch 0: TMR0
Transmit Control/Status Reg.
Ch 0: TCSR0
Transmit Fill Register
Ch 0: TFR0
Transmit Interrupt Register
Ch 0: TIR0
Transmit TDM Start ^
Ch 0
Transmit TDM Length ^
Ch 0
Transmit Time Slot Assigner
Ch 0
Clocking
Control Logic
RXC0/ TXC0/
BCL0 FSC0
GCI/SCIT Interface
From Tx
To Rx
Notes: *Not Program Accessible
^ Accessed by means of Counter Access Port
BUSCLK
Receive FIFO *
Ch 0
Receive Shift Register *
Ch 0
Receiver
State Machine
Receive Mode Register
Ch 0: RMR0
Receive Interrupt Register
Ch 0: RIR0
Receive TDM Start ^
Ch 0
Receive TDM Length ^
Ch 0
Receive Time Slot Assigner
Ch 0
Interrupt Request
HDLC Control Logic
DMA Select Register
Ch 0: DSR0
Counter Access Port
Ch 0: CAP0
Baud Rate Generator MSB ^
Ch 0
Baud Rate Generator LSB ^
Ch 0
Global HDLC Vector Register
HDLCV
Figure 31. HDLC Channel Block Diagram (One of Three Channels Shown)
RXD0
54
PRELIMINARY
DS97Z382000