Z80382 Datasheet, PDF (69/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z382 I/O REGISTER MAPS
Z80380-COMPATIBLE REGISTERS
Register Name
Assigned Vectors Base Register
Trap and Break Register
I/O Waits Register
Refresh Waits Register
Clock Control Register
Refresh Register 0
Refresh Register 1
Refresh Register 2
Standby Mode Control Register
Interrupt Enable Register
Chip Version ID Register
Z80382 ASCI, PRT, CSIO, WDT REGISTERS
Register Name
ASCI Control Register A Ch 0
ASCI Control Register A Ch 1
ASCI Control Register B Ch 0
ASCI Control Register B Ch 1
ASCI Status Register Ch 0
ASCI Status Register Ch 1
ASCI TX Data Register Ch 0
ASCI TX Data Register Ch 1
ASCI RX Data Register Ch 0
ASCI RX Data Register Ch 1
CSI/O Control Register
CSI/O Tx/Rx Data Register
Timer Data Register Ch OL
Timer Data Register Ch OH
Reload Register Ch OL
Reload Register Ch OH
Timer Control Register
Timer Prescale Register
ASCI0 Extension Control Register
ASCI1 Extension Control Register
Z80382/Z8L382
High-Performance Data Communications Processors
1
Z382 Address Z380 Address
Access
%0018
%0018
R/W
%0019
%0019
R/W
%001E
%000E
R/W
%001F
%000F
R/W
%0021
%0011
R/W
%0023
%0013
R/W
%0024
%0014
R/W
%0025
%0015
R/W
%0026
%0016
R/W
%0027
%0017
R/W
%0020
%00FF
RO
I/O Address
%0000
%0001
%0002
%0003
%0004
%0005
%0006
%0007
%0008
%0009
%000A
%000B
%000C
%000D
%000E
%000F
%0010
%0011
%0012
%0013
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DS97Z382000
PRELIMINARY
69