Z80382 Datasheet, PDF (26/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
AC CHARACTERISTICS (Continued)
HDLC Timing - Non-GCI TDM mode (See Figure 20)
Specifications apply over Standard Operating Conditions unless otherwise noted. C_L = 50 pF for outputs.
Z80382
Z8L382
Symbol
Parameter
Min.
Max.
Min.
Max.
t120 FSC Setup to BCL Fall
t121 FSC Hold from BCL Low
30
50
20
30
t122 BCL Period
50
50
t123 BCL High Time
15
15
t124 BCL Low Time
15
15
t125 BCL High to TxEN Low
15
20
t126 BCL High to TxEN High
15
20
t127 BCL High to TxD Valid
15
20
t128 BCL High to TxD Invalid
15
20
t129 RxD Setup to BCL Fall (Rise)
15
20
t130 RxD Hold from BCL Low (High)
5
5
Note: 1. Receive clock sampling edge is configurable by means of RIRn[6]. See Z80382 User Manual.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
BCL
(input)
0
FSC
(input)
TxEN
t120
t122 ^t123
1
2
3
Number of
clocks start
t121
t125
t124
t130
t126
t128
t127
TxD
t129
RxD
Figure 20. HDLC Timing - Non-GCI TDM Mode (Shown for Start = 3, Length = 2, Negative Edge RxD Sampling)
26
PRELIMINARY
DS97Z382000