Z80382 Datasheet, PDF (71/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
DMA REGISTERS
Z80382/Z8L382
High-Performance Data Communications Processors
Register Name
DMA Control Register
DMA Vector Register
DMA0 List Address Register Low*
DMA0 List Address Register Middle*
DMA0 List Address Register High*
DMA0 Control/Status Register
DMA1 List Address Register Low*
DMA1 List Address Register Middle*
DMA1 List Address Register High*
DMA1 Control/Status Register
DMA2 List Address Register Low*
DMA2 List Address Register Middle*
DMA2 List Address Register High*
DMA2 Control/Status Register
DMA3 List Address Register Low*
DMA3 List Address Register Middle*
DMA3 List Address Register High*
DMA3 Control/Status Register
DMA4 List Address Register Low*
DMA4 List Address Register Middle*
DMA4 List Address Register High*
DMA4 Control/Status Register
DMA5 List Address Register Low*
DMA5 List Address Register Middle*
DMA5 List Address Register High*
DMA5 Control/Status Register
DMA6 List Address Register Low*
DMA6 List Address Register Middle*
DMA6 List Address Register High*
DMA6 Control/Status Register
DMA7 List Address Register Low*
DMA7 List Address Register Middle*
DMA7 List Address Register High*
DMA7 Control/Status Register
I/O Address
Access
1
%003E
R/W
%003F
R/W
%0040
R/W
%0041
R/W
%0042
R/W
%0043
R/W
%0044
R/W
%0045
R/W
%0046
R/W
%0047
R/W
%0048
R/W
%0049
R/W
%004A
R/W
%004B
R/W
%004C
R/W
%004D
R/W
%004E
R/W
%004F
R/W
%0050
R/W
%0051
R/W
%0052
R/W
%0053
R/W
%0054
R/W
%0055
R/W
%0056
R/W
%0057
R/W
%0058
R/W
%0059
R/W
%005A
R/W
%005B
R/W
%005C
R/W
%005D
R/W
%005E
R/W
%005F
R/W
Note: * These addresses can be selected to access the Buffer Address and Buffer Length register for testing.
DS97Z382000
PRELIMINARY
71