Z80382 Datasheet, PDF (35/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
Table 10. Other Signals
Pin
Pin Name Number(s)
Description
1
CLKI
128 Clock/Crystal (input, active High): An externally generated clock can be input at this pin.
Alternatively, a crystal can be connected between CLKI and CLKO. In either case, the fre-
quency at this pin can be used directly as the processor clock (BUSCLK), or divided by two
or multiplied by two, under software control.
CLKO
129 CLKO Crystal (output, active High): Crystal oscillator connection.This pin should be left
open if an externally generated clock is input at the CLKI pin. Feedback on this pin can be
disabled by software to save power and noise when an external clock is used.
IEI
47
Interrupt Enable In (input, active High): If external devices are connected to /INT0, and
should have higher interrupt priority than the on-chip Mimic, DMAs, and HDLC controllers,
this signal should be connected to the IEO output of the lowest-priority among such devic-
es.
IEO
48
Interrupt Enable Out (output, active high): If external devices are connected to /INT0, and
should have lower interrupt priority than the on-chip Mimic, DMAs, and HDLC controllers,
this signal should be connected to the IEI input of the highest-priority such device.
V_DD
5, 23, 41, 59, Power Supply: These eight pins carry power to the device. They must be tied to the same
77, 95, 113, voltage externally.
131
V_SS
14, 32, 50, 68, Ground: These eight pins are the ground references for the device.They must be tied to
86, 104, 122, the same voltage externally.
140
FUNCTIONAL DESCRIPTION
The functional blocks within the Z382 can be broadly iden-
tified as central processing unit, host interface, serial com-
munication channels, DMA control, timers and counters,
and system interface logic. Each of these blocks will be fur-
ther described in the sections which follow.
For additional information, please refer to the Z382 UserÕs
Manual, available from your Zilog representative or distrib-
utor.
CENTRAL PROCESSING UNIT
The Central Processing Unit (CPU) core of the Z382 is the
380C (Z380), which is a binary-compatible extension of
the Z80^¨ and Z180^ª CPU architectures. High throughput
rates for the 380C are achieved by a high clock rate, high
bus bandwidth and instruction fetch/execute overlap.
Communicating to the external world through an 8- or 16-
bit data bus, the 380C is a full 32-bit machine internally,
with a 32-bit ALU and 32-bit registers.
Modes of Operation
The 380C can operate in either Native or Extended mode,
as controlled by a bit in the Select Register (SR). In Native
mode (the default configuration after Reset), all address
manipulations are performed modulo 65536 (16 bits). In
this mode the Program Counter (PC) only increments
across 16 bits, all address manipulation instructions (incre-
ment, decrement, add, subtract, indexed, stack relative,
and PC relative) only operate on 16 bits, and the Stack
Pointer (SP) only increments and decrements across 16
bits. The program counter high-order word is left at all ze-
ros, as are the high-order words of the stack pointer and
the I register. Thus, Native mode is fully compatible with
the Z80 CPU's 64 KB address space. It is still possible to
address memory outside of the 64 KB address space for
data storage and retrieval in Native mode, however, as di-
rect addresses, indirect addresses, and the high-order
word of the SP, I and the IX and IY registers may be loaded
with non-zero values. But executed code and interrupt ser-
vice routines must reside in the lowest 64 KB of the ad-
dress space.
In Extended mode, all address manipulation instructions
operate on 32 bits, potentially allowing access to a 4 GB
address space. In both Native and Extended modes, how-
ever, the Z382 outputs only 24 bits of the address onto the
external address bus, limiting the actual usable address
space to 16 MB. Only the width of manipulated addresses
distinguish Native from Extended mode. The 380C imple-
ments one instruction to allow switching from Native to Ex-
tended mode, but once in Extended mode, only Reset re-
turns the CPU to Native mode. This restriction applies
DS97Z382000
PRELIMINARY
35