Z80382 Datasheet, PDF (30/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
PIN FUNCTIONS (Continued)
Pin Name
IOCLK
Table 4. MPU Signals
Pin
Number(s)
Description
114 I/O Clock (output, active High, tri-state): This signal is a program controlled divided-down
version of BUSCLK. The division factor can be two, four, six or eight with I/O transactions
and interrupt-acknowledge transactions occurring relative to IOCLK. IOCLK can be dis-
abled, in which case BUSCLK is the timing reference for I/O transactions.
/IORQ
/IORD
/IOWR
/IOCS1
/IOCS2
/M1
/MRD
/MSIZE
Note: The INTACK output of the Z380 has been omitted on the Z382 for pinning reasons.
A similar signal can be easily obtained by low-active-ANDing (positive-logic ORing) the
/M1 and /IORQ outputs.
115 Input/Output Request (output, active Low, tri-state): This signal is active during all I/O
read and write transactions and interrupt acknowledge transactions.
125 Input/Output Read Strobe (output, active Low, tri-state): This signal is used to strobe
data from the peripherals during I/O read transactions.
123 Input/Output Write Strobe (output, active Low, tri-state): This signal is used to strobe
data into the peripherals during I/O write transactions.
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I/O Chip Select (output, active Low): These outputs may be used to access external I/O
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devices. The base I/O address and range are programmable.
116 Machine Cycle One (output, active Low, tri-state): This signal is active during instruction
fetch and interrupt acknowledge transactions. Note that the Z382 does not support RETI
decoding by Z80 peripherals (PIO), SIO, and CTC. It does support Z80-type interrupt dai-
sy-chaining by devices that include explicit clearing of IUS (for example, SCC).
126 Memory Read (output, active Low, tri-state): This signal indicates that the addressed
memory location should place its data on the data bus. /MRD is active from the end of T1
until the end of T4 during memory read transactions.
117 Memory Size (input/open-drain output, active Low): In 16-bit memory operations, this sig-
nal indicates whether the addressed memory location is word size (logic High) or byte size
(logic Low). In the latter case, the 8-bit memory should be connected to the D7-0 lines, and
an additional memory transaction on D7-0 will automatically be generated to transfer the
other byte of the word. (See the note on pin name swapping after the /BLEN pin descrip-
tion.) /MSIZE is driven as an open-drain output by the memory decoding modules, when
they are enabled in 8-bit mode and the address falls within their range.
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PRELIMINARY
DS97Z382000