Z80382 Datasheet, PDF (60/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
Zilog
SERIAL COMMUNICATION CHANNELS (Continued)
a timing request from the downstream unit (the pin being
pulled Low).
Deactivation Request, Downstream to Upstream: De-
activation is normally initiated by the upstream device as
described above. When the downstream device receives
the deactivation request over the C/I0 channel, it must re-
spond by sending the deactivation indication.
Activation Request, Downstream to Upstream: The
downstream device can request that the clocks be started
by pulling its data output line low. Once the clocks are
started, the downstream unit requests activation by send-
ing an activation request over the C/I0 channel.
Activation, Upstream to Downstream: The upstream
unit activates the bus by starting the clocks and following
the C/I0 channel-based activation procedure.
B1, B2, D, IC1, IC2 Channel Data: Rx data and the bit
clock are supplied to the HDLC cells, and Tx data is taken
from the HDLC cells. Each HDLC Transmitter and Receiv-
er includes a Time Slot Assigner which can be pro-
grammed for any of the subchannels shown above.
Note: The HDLC Transmitters signal when they are
sending data. This signalling should not conflict with
transmission by the GCI/SCIT module, but if it should, the
HDLC modules have priority.
GCI/SCIT Registers
The GCI/SCIT interface includes the following I/O-mapped
registers that can be read and written by the 380C proces-
sor:
s GCI Control Register
s Monitor 0 Transmit Data Register
s Monitor 0 Receive Data Register
s Monitor 1 Transmit Data Register
s Monitor 1 Receive Data Register
s C/I0 - C/I2 Transmit Data Register
s C/I0 - C/I2 Receive Data Register
s C/I1 Transmit Data Register
s C/I1 Receive Data Register
s GCI Status Register 1
s GCI Status Register 2
s GCI Interrupt Enable Register
GCI Control Register. Controls the Monitor 1 and C/I1 Di-
rection, the clock activation request to the master, en-
abling/disabling Monitors 1 and 0, and Monitors 1 and 0
EOM and Abort requests.
Monitor 0, Monitor 1, C/I0 - C/I2 and C/I1Transmit Data
Registers. Data written into these registers is transmitted
on the respective channels in accordance with the
GCI/SCIT protocol.
Monitor 0, Monitor 1, C/I0 - C/I2 and C/I1Receive Data
Registers. Data received from the respective channels in
accordance with the GCI/SCIT protocol is written into
these registers.
GCI Status Register 1. Provides receive and transmit sta-
tus conditions for Monitor 0 and 1 channels.
GCI Status Register 2. Provides additional status condi-
tions for the GCI/SCIT module.
GCI Interrupt Enable Register. Provides control of inter-
rupts from the various channels in the GCI/SCIT module.
Clocked Serial I/O (CSIO)
The Z382 includes a synchronous serial I/O port (CSI/O)
which provides half-duplex transmission/reception of fixed
8-bit data at a speed of up to BUSCLK/20 bits/second. The
CSI/O is ideal for implementing a multiprocessor commu-
nication link between multiple Z80xxx family members. A
block diagram of the CSI/O is illustrated below.
Internal Address/Data Bus
TXS
RXS
CSI/O Transmit/Receive
Data Register:
TRDR
CSI/O Control Register:
CNTR
Interrupt Request
Baud Rate
Generator
CKS
f
Figure 34. CSI/O Block Diagram
Note that the three pins associated with the CSI/O are mul-
tiplexed with other signals and must be configured for
CSI/O operation in order to use the CSI/O as described in
this section.
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PRELIMINARY
DS97Z382000