Z80382 Datasheet, PDF (40/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
HOST INTERFACE (Continued)
Mimic Receiver FIFO
The receiver FIFO is 16-words deep and stores eight data
bits and three error bits (Parity error, Framing error and
Break detect) for each character received. The data and
error bits move together in the FIFO. The error bits be-
come available to the Host side of the interface when that
particular location becomes the next address to read (top
of FIFO). At that time they may either be read by the Host
or they may cause an interrupt to the Host interface if so
enabled. The error bits are set by the error status of the
byte at the top of the FIFO but may only be cleared by
reading the Line Status Register (LSR). If successive
reads of the receiver FIFO are performed without reading
the LSR, the status bits will be set if any of the bytes read
have the respective error bit set.
The Host interface may be interrupted when 1, 4, 8 or 14
bytes are available in the receiver FIFO. If the FIFO is not
Zilog
empty, but below the programmed trigger value, a timeout
interrupt is available if the receiver FIFO is not written by
the 380C or read by the Host by an interval determined by
the Character Timeout Timer. This is an additional timer
with 380C access only which is used to emulate the 16550
four-character timeout delay. The timer receives the BRG
as its input clock. Software must determine the correct val-
ues to program into the Receiver Timeout Register and the
BRG to achieve the correct delay interval for timeout.
These interrupts are cleared by the FIFO reaching the trig-
ger point or by resetting the Timeout interval timer by a
FIFO 380C write or Host read access.
With FIFO mode enabled, the 380C is interrupted when
the receiver FIFO is empty. This bit corresponds to a Host
read of the receiver buffer in non-FIFO (16450) mode. The
interrupt source is cleared when the FIFO becomes non-
empty or the 380C reads the IUS/IP register.
MPU Write
LSR Shadow
B2-B4
3
3
PC Read
LSR Shadow
B2-B4
Internal Clock
Internal Clock
MPU
Control
Line
Sync
MPU Databus
(MPU Side
8
Write)
Internal
Clock
16 x 8
Data Bits
Write
ALU
Pointer
16 x 3
Error
Bits
Read
Pointer
Sync
8
5
PC Control
Line
PC Databus
(PC Side
Read)
FIFO Control
Register
MPU IRQ
PC IRQ
Figure 24. 16550 Mimic Receiver FIFO Block Diagram
40
PRELIMINARY
DS97Z382000