Z80382 Datasheet, PDF (31/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
Table 4. MPU Signals
Pin
Pin Name Number(s)
Description
1
/MWR
124 Memory Write (output, active Low, tri-state): This signal indicates that the addressed
memory location should store the data on the databus, as qualified by /BHEN and /BLEN.
/MWR is active from the end of T2 until the end of T4 during memory write transactions.
/NMI
135 Nonmaskable Interrupt (input, falling edge-triggered): This input has higher priority than
the maskable interrupt inputs /INT3-/INT0.
/RESET
134 Reset (input, active Low): This input must be active for a minimum of five BUSCLK periods
to initialize the Z382. The effect of /RESET is described in detail in the Reset section.
/ROMCS
42
ROM Chip Select (output, active Low): After Reset, the Z382 drives this output and
/MSIZE Low for all memory accesses with A23=0. Software can program the chip select
logic to assert /ROMCS for a different range of memory addresses. If ROM is 16 bits wide
and composed of two 8-bit devices, connect the Chip Select inputs of both devices to
/ROMCS, and program the hardware not to force /MSIZE Low in the first two instructions
of the ROM code.
/RAMCSL
43
RAM Chip Select Low, High (outputs, active Low): After Reset, the Z382 drives /RAMC-
/RAMCSH
44
SL and /MSIZE Low for memory cycles with A23=1, and puts the /RAMCSH pin under con-
trol of its alternate use (a port pin). If RAM is only eight bits wide, connect its Chip Select
input to /RAMCSL. If RAM is 16 bits wide, connect one of these pins to the chip select of
each 8-bit RAM, and reprogram the hardware not to force /MSIZE Low, in which case
/RAMCSL is qualified with /BLEN, and /RAMCSH is qualified with /BHEN. On the Z382
these signals have the same timing as address lines, so there is no timing penalty for this
qualification.
/TREFA
111 Timing Reference A (output, active Low, tri-state): This timing reference signal goes Low
at the end of T2 and returns High at the end of T4 during a memory read, memory write or
refresh transaction. It can be used to control the address multiplexer for a DRAM interface
or as the /RAS signal at higher processor clock rates.
/TREFC
110 /Timing Reference C (output, active Low, tri-state): This timing reference signal goes Low
at the end of T3 and returns High at the end of T4 during a memory read, memory write or
refresh transaction. It can be used as the /CAS signal for DRAM accesses.
/TREFR
112 Timing Reference R (output, active Low, tri-state): This timing reference signal goes Low
at the end of T1 and returns High at the end of T4 during a memory read, memory write or
refresh transaction. It can be used as the /RAS signal for DRAM accesses.
/WAIT
130 Wait (input, active Low): This input is sampled by BUSCLK or IOCLK, as appropriate, to
insert Wait states into the current bus transaction.
.
Pin Name
CKA0
CKA1
/CTS0
/CTS1
/DCD0
/DCD1
Table 5. UART, Timer and CSIO Signals
Pin
Number(s)
Description
53/92/96
49/65/100
61/111
60/110
89/112
66
Asynchronous Clock 0, 1 (Bidirectional): Clock signals to or from the asynchronous
channels (ASCIs).
Clear to Send 0, 1 (Inputs, active Low): Transmit control signals for the ASCI channels.
Data Carrier Detect 0, 1 (Inputs, active Low): Receive control signals for the ASCI chan-
nels. /DCD1 is not available in ISA applications.
DS97Z382000
PRELIMINARY
31