Z80382 Datasheet, PDF (53/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
ASCI Register Set
Software can select whether each channelÕs I/O is on de-
Each ASCI contains a set of registers for programming vice pins or on the internal TDM highway (the GCI/SCIT
various aspects of its operation. These registers are:
1 ^{bus in the Z382). If device pins are used, they can be con-}
figured as either a classic synchronous serial interface, or
s Control Register A
s Control Register B
as the interface to an external TDM highway or highways.
The differences in pin use are as follows:
s Time Constant High Register
s Time Constant Low Register
s Extension Control Register
s Status Register
s Receive Data Register
s Transmit Data Register
s DMA Control Register
s Control Register A
Pin
TDM Operation
Full Time
Operation
TxD
Tri-stated outside the timeDriven full time
slot.
RxD
Sampled within the time Sampled in every
slot.
bit time
RxC/BCL Common clock for Rx and Rx Clock, optional
Tx.
Tx Clock
HDLC Serial Channels
TxC/FSC Frame Sync pulse for Rx Tx Clock in or out.
and Tx.
The Z382 features three high-speed serial channels, each
comprised of a transmitter and a receiver, which can oper-
ate in HDLC or transparent (unframed) modes. All data
transfers to and from the HDLC channels are carried out
TxEN
Asserted within the time Asserted
slot, optional enable for an whenever Tx is
external driver.
enabled.
by the DMA channels. Thus, each HDLC channel must
have an assigned DMA channel to perform its function. Fa-
cilities for interrupt-driven or polled transfer of HDLC data
are not provided.
Eight-character FIFOs on both the transmit and receive
side reduce the possibility of overrun and underrun condi-
tions to a minimum, at data rates up to and beyond E1
(2.048 Mbps).
DS97Z382000
PRELIMINARY
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