Z80382 Datasheet, PDF (28/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Z80382/Z8L382
High-Performance Data Communications Processors
AC CHARACTERISTICS (Continued)
t131
DCL
t140
FSC
DU/DD
transmit
DU/DD
receive
t133
t134
t131
t132
t135
t137
t136
t138
3
t139
Figure 21. GCI/SCIT Slave and Master Timing
Zilog
PIN FUNCTIONS
The tables which follow describe the input and output sig-
nals of the Z382. Signals are normally asserted in the High
state and negated in the Low state. A hyphen (/) preceding
the signal name indicates that the signal is asserted in the
Low state and negated in the High state.
Many pins have multiple functions, and thus may appear
more than once in the pin description tables. In each table,
such pins are described using their function in that mode.
Likewise, some signals may be output on alternate pins
depending on the mode under which the Z382 is operating.
The notation Òxx/yyÓ in the Pin Number column indicates
that the signal may be assigned to pin ÒxxÓ or pin ÒyyÓ.
28
PRELIMINARY
DS97Z382000