Z80382 Datasheet, PDF (55/77 Pages) Zilog, Inc. – HIGH-PERFORMANCE DATA COMMUNICATIONS PROCESSORS

Zilog
Z80382/Z8L382
High-Performance Data Communications Processors
Interface with a Common TDM Module (for example,
Type/Status Bytes in Transmitter DMA Lists. In HDLC
GCI/SCIT)
mode, a frame to be transmitted can be contained in one
1 ^{The interface between an HDLC channel and the or more DMA buffers. The DMA list entry for the last (or}
GCI/SCIT module includes:
only) buffer of a frame should have its Type/Status byte
coded as ÒReady Buffer, notify at End of BufferÓ. This
TxD A bused line onto which HDLC Transmitters place ^{makes the Transmitter send the CRC (if enabled) and a}
data in their time slots, as directed by software
closing Flag after the last byte of the buffer. Buffers that do
programming.
not include the end of a frame should have their Type/Sta-
RxD A bused line from which HDLC Receivers take
data in their time slots, as directed by software
tus bytes coded as ÒReady Buffer, no End of Buffer Notifi-
cationÓ.
programming.
BCL A common bit clock for HDLC Transmitters and
Receivers. Transmitters change data on TxD on
falling edges of BCL, and Receivers sample data
Two control fields for the Transmitter do not reside in pro-
cessor-accessible register bits, but can be controlled sep-
arately for each frame in Type/Status bytes in the DMA list:
FSC
from RxD on rising edges of BCL.
Frame Sync, synchronous to BCL. Transmitters
and Receivers measure their time slots
independently from the rising edge of this signal.
The duration of FSC can be one or more BCL
1. How many bits the Transmitter sends from the last
byte of the frame.
2. Whether the Transmitter sends its accumulated CRC
at the end of the frame.
TxEN
cycles.
An output from each Transmitter to the common
TDM module, indicating its time slot, that is, when
it is placing data on TxD.
Either of these items can be changed automatically from
one frame to the next if the Type/Status byte for the frame
is coded as ÒReady Buffer, with CommandÓ and the control
bits of that byte are set appropriately.
TDM Processing
When the Transmit (Receive) TDM Length register is non-
zero, the Transmitter (Receiver) activates its Time Slot As-
signer to clock Tx (Rx) data only within the time slot. If a
TDM Start register is non-zero, then after each pulse on
Frame Sync, the Time Slot Assigner blocks clocking for the
number of bits specified by the TDM Start register. Then,
or immediately at Frame Sync if the Start value is zero, it
enables clocking for the number of bits specified by the
TDM Length register. Thereafter, it again blocks clocking
until the next Frame Sync pulse. For example, the Start
and Length values for the GCI subchannels are:
In HDLC modes or in Transparent mode with the Underrun
Wait bit set to 1, completed Buffer codes in Type/Status
bytes in Transmitter DMA lists are stored as Òwith StatusÓ
if the Transmitter encountered an Underrun while sending
the data in the buffer. In all other cases, Type/Status bytes
in Transmitter DMA lists are stored as Òno status.Ó
Type/Status Bytes in Receiver DMA Lists. HDLC re-
ceivers do not use the Command nor End of Buffer notifi-
cation features of the DMA channels. Thus all ÒReady Buff-
erÓ codes in Type/Status bytes in Receiver DMA lists are
equivalent.
Channel
B1 (64K bps)
B1 (56K)
B2 (64K)
B2 (56K)
D
IC1
IC2
Start
0
0
8
8
24
32
40
Length
8
7
8
7
2
8
8
Type/Status Bytes in DMA Lists
Note: Please refer to the description of Type/Status bytes
in the section on the DMA channels in conjunction with this
topic.
A received frame can be contained in one DMA buffer, or
can span two or more buffers. The end of a frame always
makes the Receiver terminate its current DMA buffer and
store frame status in its Type/Status byte.
When a buffer is filled with receive data, without the last
character of the frame being stored in that buffer, that buff-
erÕs Type/Status byte is stored as ÒCompleted Buffer (no
Status)Ó. Buffers that include the last character of a frame,
and buffers that couldnÕt be completed because the Re-
ceiver encountered an Overrun condition, are stored as
ÓCompleted Buffer (with Status)Ó. The least significant five
bits of such a Type/Status byte indicate the status of the
buffer.
DS97Z382000
PRELIMINARY
55