DS003-1 Datasheet, PDF (9/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
COUT
G4
G3
G2
G1
BY
F5IN
BX
F4
F3
F2
F1
SR
CLK
CE
CY
I3
I2
LUT
O
I1
I0
WE
DI
0
1
CY
CK WSO
WE
A4 WSH
BY DG
BX DI
I3
WE
DI
I2
O
I1
LUT
I0
0
1
F6
F5
YB
Y
INIT
DQ
YQ
EC
REV
XB
F5
X
INIT
DQ
XQ
EC
REV
CIN
viewslc4.eps
Figure 5: Detailed View of VIrtex Slice
Additional Logic
The F5 multiplexer in each slice combines the function gen-
erator outputs. This combination provides either a function
generator that can implement any 5-input function, a 4:1
multiplexer, or selected functions of up to nine inputs.
Similarly, the F6 multiplexer combines the outputs of all four
function generators in the CLB by selecting one of the
F5-multiplexer outputs. This permits the implementation of
any 6-input function, an 8:1 multiplexer, or selected func-
tions of up to 19 inputs.
Each CLB has four direct feedthrough paths, one per LC.
These paths provide extra data input lines or additional local
routing that does not consume logic resources.
Arithmetic Logic
Dedicated carry logic provides fast arithmetic carry capabil-
ity for high-speed arithmetic functions. The Virtex CLB sup-
ports two separate carry chains, one per Slice. The height
of the carry chains is two bits per CLB.
The arithmetic logic includes an XOR gate that allows a
1-bit full adder to be implemented within an LC. In addition,
a dedicated AND gate improves the efficiency of multiplier
implementation.
The dedicated carry path can also be used to cascade func-
tion generators for implementing wide logic functions.
BUFTs
Each Virtex CLB contains two 3-state drivers (BUFTs) that
can drive on-chip busses. See Dedicated Routing, page 7.
Each Virtex BUFT has an independent 3-state control pin
and an independent input pin.
Block SelectRAM
Virtex FPGAs incorporate several large block SelectRAM
memories. These complement the distributed LUT
SelectRAMs that provide shallow RAM structures imple-
mented in CLBs.
Block SelectRAM memory blocks are organized in columns.
All Virtex devices contain two such columns, one along
each vertical edge. These columns extend the full height of
the chip. Each memory block is four CLBs high, and conse-
quently, a Virtex device 64 CLBs high contains 16 memory
blocks per column, and a total of 32 blocks.
Table 3 shows the amount of block SelectRAM memory that
is available in each Virtex device.
Table 3: Virtex Block SelectRAM Amounts
Device # of Blocks Total Block SelectRAM Bits
XCV50
8
32,768
XCV100
10
40,960
XCV150
12
49,152
XCV200
14
57,344
XCV300
16
65,536
XCV400
20
81,920
XCV600
24
98,304
XCV800
28
114,688
XCV1000
32
131,072
DS003-2 (v2.8.1) December 9, 2002
Product Specification
www.xilinx.com
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