DS003-1 Datasheet, PDF (34/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
Calculation of T_ioop as a Function of
Capacitance
T_ioop is the propagation delay from the O Input of the IOB to
the pad. The values for T_ioop were based on the standard
capacitive load (Csl) for each I/O standard as listed in
Table 2.
Table 2: Constants for Calculating T_ioop
Standard
Csl
fl
(pF) (ns/pF)
LVTTL Fast Slew Rate, 2mA drive
35
0.41
LVTTL Fast Slew Rate, 4mA drive
35
0.20
LVTTL Fast Slew Rate, 6mA drive
35
0.13
LVTTL Fast Slew Rate, 8mA drive
35
0.079
LVTTL Fast Slew Rate, 12mA drive
35
0.044
LVTTL Fast Slew Rate, 16mA drive
35
0.043
LVTTL Fast Slew Rate, 24mA drive
35
0.033
LVTTL Slow Slew Rate, 2mA drive
35
0.41
LVTTL Slow Slew Rate, 4mA drive
35
0.20
LVTTL Slow Slew Rate, 6mA drive
35
0.100
LVTTL Slow Slew Rate, 8mA drive
35
0.086
LVTTL Slow Slew Rate, 12mA drive
35
0.058
LVTTL Slow Slew Rate, 16mA drive
35
0.050
LVTTL Slow Slew Rate, 24mA drive
35
0.048
LVCMOS2
35
0.041
PCI 33MHz 5V
50
0.050
PCI 33MHZ 3.3 V
10
0.050
PCI 66 MHz 3.3 V
10
0.033
GTL
0
0.014
GTL+
0
0.017
HSTL Class I
20
0.022
HSTL Class III
20
0.016
HSTL Class IV
20
0.014
SSTL2 Class I
30
0.028
SSTL2 Class II
30
0.016
SSTL3 Class I
30
0.029
SSTL3 Class II
30
0.016
CTT
20
0.035
AGP
10
0.037
Notes:
1. I/O parameter measurements are made with the capacitance
values shown above. See Application Note XAPP133 on
www.xilinx.com for appropriate terminations.
2. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
For other capacitive loads, use the formulas below to calcu-
late the corresponding T_ioop.
T_ioop = T_ioop + T_opadjust + (C_load – C_sl) * fl
Where:
T_opadjust is reported above in the Output Delay
Adjustment section.
C_load is the capacitive load for the design.
Table 3: Delay Measurement Methodology
Standard
LVTTL
V_L ⁽¹⁾
0
V_H ⁽¹⁾
3
Meas. V_REF
Point Typ⁽²⁾
1.4
-
LVCMOS2
0
2.5
1.125
-
PCI33_5
Per PCI Spec
-
PCI33_3
Per PCI Spec
-
PCI66_3
Per PCI Spec
-
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 I & II
SSTL2 I & II
CTT
AGP
V_REF –0.2
V_REF –0.2
V_REF –0.5
V_REF –0.5
V_REF –0.5
V_REF –1.0
V_REF –0.75
V_REF –0.2
V_REF –
(0.2xV_CCO)
V_REF +0.2
V_REF +0.2
V_REF +0.5
V_REF +0.5
V_REF +0.5
V_REF +1.0
V_REF +0.75
V_REF +0.2
V_REF +
(0.2xV_CCO)
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
0.80
1.0
0.75
0.90
0.90
1.5
1.25
1.5
Per
AGP
Spec
Notes:
1. Input waveform switches between V_Land V_H.
2. Measurements are made at VREF (Typ), Maximum, and
Minimum. Worst-case values are reported.
3. I/O parameter measurements are made with the capacitance
values shown in Table 2. See Application Note XAPP133 on
www.xilinx.com for appropriate terminations.
4. I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
Module 3 of 4
10
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DS003-3 (v3.2) September 10, 2002
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