DS003-1 Datasheet, PDF (19/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
FPGA starts to clear
configuration memory.
FPGA makes a final
clearing pass and releases
INIT when finished.
Apply Power
Set PROGRAM = High
Release INIT
If used to delay
configuration
INIT? ^Low
High
Load a Configuration Bit
Once per bitstream,
FPGA checks data using CRC
and pulls INIT Low on error.
End of
No
Bitstream?
If no CRC errors found,
FPGA enters start-up phase
causing DONE to go High.
Yes
Configuration Completed
ds003_154_111799
Figure 15: Serial Configuration Flowchart
After configuration, the pins of the SelectMAP port can be
used as additional user I/O. Alternatively, the port can be
retained to permit high-speed 8-bit readback.
Retention of the SelectMAP port is selectable on a
design-by-design basis when the bitstream is generated. If
retention is selected, PROHIBIT constraints are required to
prevent the SelectMAP-port pins from being used as user
I/O.
Table 9: SelectMAP Write Timing Characteristics
Description
D_0-7 Setup/Hold
CS Setup/Hold
CCLK
WRITE Setup/Hold
BUSY Propagation Delay
Maximum Frequency
Maximum Frequency with no handshake
Multiple Virtex FPGAs can be configured using the Select-
MAP mode, and be made to start-up simultaneously. To
configure multiple devices in this way, wire the individual
CCLK, Data, WRITE, and BUSY pins of all the devices in
parallel. The individual devices are loaded separately by
asserting the CS pin of each device in turn and writing the
appropriate data. See Table 9 for SelectMAP Write Timing
Characteristics.
.
Symbol
Units
1/2
T_SMDCC/T_SMCCD
5.0 / 1.7 ns, min
3/4
T_SMCSCC/T_SMCCCS
7.0 / 1.7
ns, min
5/6
T_SMCCW/T_SMWCC
7.0 / 1.7
ns, min
7
T_SMCKBY
12.0
ns, max
F_CC
66
MHz, max
F_CCNH
50
MHz, max
Write
Write operations send packets of configuration data into the
FPGA. The sequence of operations for a multi-cycle write
operation is shown below. Note that a configuration packet
can be split into many such sequences. The packet does
not have to complete within one assertion of CS, illustrated
in Figure 16.
1. Assert WRITE and CS Low. Note that when CS is
asserted on successive CCLKs, WRITE must remain
either asserted or de-asserted. Otherwise an abort will
be initiated, as described below.
2. Drive data onto D[7:0]. Note that to avoid contention,
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.
DS003-2 (v2.8.1) December 9, 2002
Product Specification
www.xilinx.com
1-800-255-7778
Module 2 of 4
15