DS003-1 Datasheet, PDF (49/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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DS003-4 (v2.8) July 19, 2002
Virtex Pin Definitions
Table 1: Special Purpose Pins
Pin Name
Dedicated
Pin
GCK0, GCK1,
Yes
GCK2, GCK3
M0, M1, M2
Yes
CCLK
Yes
PROGRAM
Yes
DONE
Yes
INIT
No
BUSY/
No
DOUT
D0/DIN,
No
D1, D2,
D3, D4,
D5, D6,
D7
WRITE
No
CS
No
TDI, TDO,
Yes
TMS, TCK
DXN, DXP
Yes
V_CCINT
Yes
V_CCO
Yes
V_REF
No
GND
Yes
0
Virtex™ 2.5 V
Field Programmable Gate Arrays
0 0 _{Production Product Specification}
Direction
Input
Input
Input or
Output
Input
Bidirectional
Bidirectional
(Open-drain)
Output
Input or
Output
Input
Input
Mixed
Description
Clock input pins that connect to Global Clock Buffers. These pins become
user inputs when not needed for clocks.
Mode pins are used to specify the configuration mode.
The configuration Clock I/O pin: it is an input for SelectMAP and
slave-serial modes, and output in master-serial mode. After configuration,
it is input only, logic level = Don’t Care.
Initiates a configuration sequence when asserted Low.
Indicates that configuration loading is complete, and that the start-up
sequence is in progress. The output can be open drain.
When Low, indicates that the configuration memory is being cleared. The
pin becomes a user I/O after configuration.
In SelectMAP mode, BUSY controls the rate at which configuration data
is loaded. The pin becomes a user I/O after configuration unless the
SelectMAP port is retained.
In bit-serial modes, DOUT provides header information to downstream
devices in a daisy-chain. The pin becomes a user I/O after configuration.
In SelectMAP mode, D0 - D7 are configuration data pins. These pins
become user I/Os after configuration unless the SelectMAP port is
retained.
In bit-serial modes, DIN is the single data input. This pin becomes a user
I/O after configuration.
In SelectMAP mode, the active-low Write Enable signal. The pin becomes
a user I/O after configuration unless the SelectMAP port is retained.
In SelectMAP mode, the active-low Chip Select signal. The pin becomes
a user I/O after configuration unless the SelectMAP port is retained.
Boundary-scan Test-Access-Port pins, as defined in IEEE 1149.1.
N/A
Input
Input
Input
Input
Temperature-sensing diode pins. (Anode: DXP, cathode: DXN)
Power-supply pins for the internal core logic.
Power-supply pins for the output drivers (subject to banking rules)
Input threshold voltage pins. Become user I/Os when an external
threshold voltage is not needed (subject to banking rules).
Ground
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DS003-4 (v2.8) July 19, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
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