DS003-1 Datasheet, PDF (32/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
Speed Grade
Description
Symbol
Min
-6
-5
-4
Units
Clock CLK to Pad delay with OBUFT
enabled (non-3-state)
T_IOCKP
1.0
2.9
3.2
3.5 ns, max
Clock CLK to Pad high-impedance
(synchronous)⁽¹⁾
T_IOCKHZ
1.1
2.3
2.5
2.9 ns, max
Clock CLK to valid data on Pad delay, plus
enable delay for OBUFT
T_IOCKON
1.5
3.4
3.7
4.1 ns, max
Setup and Hold Times before/after Clock CLK⁽²⁾
Setup Time / Hold Time
O input
OCE input
SR input (OFF)
3-State Setup Times, T input
3-State Setup Times, TCE input
3-State Setup Times, SR input (TFF)
Set/Reset Delays
T_IOOCK/T_IOCKO
T_IOOCECK/T_IOCKOCE
T_IOSRCKO/T_IOCKOSR
T_IOTCK/T_IOCKT
T_IOTCECK/T_IOCKTCE
T_IOSRCKT/T_IOCKTSR
0.51 / 0
0.37 / 0
0.52 / 0
0.34 / 0
0.41 / 0
0.49 / 0
1.1 / 0
0.8 / 0
1.1 / 0
0.7 / 0
0.9 / 0
1.0 / 0
1.2 / 0
0.9 / 0
1.2 / 0
0.8 / 0
0.9 / 0
1.1 / 0
1.3 / 0
1.0 / 0
1.4 / 0
0.9 / 0
1.1 / 0
1.3 / 0
ns, min
ns, min
ns, min
ns, min
ns, min
ns, min
SR input to Pad (asynchronous)
SR input to Pad high-impedance
(asynchronous)⁽¹⁾
T_IOSRP
T_IOSRHZ
1.6
3.8
4.1
4.6 ns, max
1.6
3.1
3.4
3.9 ns, max
SR input to valid data on Pad
(asynchronous)
T_IOSRON
2.0
4.2
4.6
5.1 ns, max
GSR to Pad
T_IOGSRQ
4.9
9.7
10.9
12.5 ns, max
Notes:
1. 3-state turn-off delays should not be adjusted.
2. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
Module 3 of 4
8
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DS003-3 (v3.2) September 10, 2002
Production Product Specification