DS003-1 Datasheet, PDF (22/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
CCLK
CS
WRITE
DATA[0:7]
BUSY
Abort
X8797_c
Figure 18: SelectMAP Write Abort Waveforms
Boundary-Scan Mode
In the boundary-scan mode, configuration is done through
the IEEE 1149.1 Test Access Port. Note that the
PROGRAM pin must be pulled High prior to reconfiguration.
A Low on the PROGRAM pin resets the TAP controller and
no JTAG operations can be performed.
Configuration through the TAP uses the CFG_IN instruc-
tion. This instruction allows data input on TDI to be con-
verted into data packets for the internal configuration bus.
The following steps are required to configure the FPGA
through the boundary-scan port (when using TCK as a
start-up clock).
1. Load the CFG_IN instruction into the boundary-scan
instruction register (IR)
2. Enter the Shift-DR (SDR) state
3. Shift a configuration bitstream into TDI
4. Return to Run-Test-Idle (RTI)
5. Load the JSTART instruction into IR
6. Enter the SDR state
7. Clock TCK through the startup sequence
8. Return to RTI
Configuration and readback via the TAP is always available.
The boundary-scan mode is selected by a <101> or 001>
on the mode pins (M2, M1, M0). For details on TAP charac-
teristics, refer to XAPP139.
Configuration Sequence
The configuration of Virtex devices is a three-phase pro-
cess. First, the configuration memory is cleared. Next, con-
figuration data is loaded into the memory, and finally, the
logic is activated by a start-up process.
Configuration is automatically initiated on power-up unless
it is delayed by the user, as described below. The configura-
tion process can also be initiated by asserting PROGRAM.
The end of the memory-clearing phase is signalled by INIT
going High, and the completion of the entire process is sig-
nalled by DONE going High.
The power-up timing of configuration signals is shown in
Figure 19. The corresponding timing characteristics are
listed in Table 10.
V_CC
TPOR
PROGRAM
INIT
TPI
CCLK OUTPUT or INPUT
TICCK
M0, M1, M2
(Required)
VALID
98122302
Figure 19: Power-Up Timing Configuration Signals
Table 10: Power-up Timing Characteristics
Description
Symbol Value
Power-on Reset
Program Latency
CCLK (output) Delay
T_POR
T_PL
T_ICCK
2.0
100.0
0.5
4.0
Program Pulse Width T_PROGRAM 300
Units
ms, max
µs, max
µs, min
µs, max
ns, min
Delaying Configuration
INIT can be held Low using an open-drain driver. An
open-drain is required since INIT is a bidirectional
open-drain pin that is held Low by the FPGA while the con-
figuration memory is being cleared. Extending the time that
the pin is Low causes the configuration sequencer to wait.
Thus, configuration is delayed by preventing entry into the
phase where data is loaded.
Start-Up Sequence
The default Start-up sequence is that one CCLK cycle after
DONE goes High, the global 3-state signal (GTS) is released.
This permits device outputs to turn on as necessary.
One CCLK cycle later, the Global Set/Reset (GSR) and Glo-
bal Write Enable (GWE) signals are released. This permits
the internal storage elements to begin changing state in
response to the logic and the user clock.
The relative timing of these events can be changed. In addi-
tion, the GTS, GSR, and GWE events can be made depen-
dent on the DONE pins of multiple devices all going High,
forcing the devices to start in synchronism. The sequence
can also be paused at any stage until lock has been
achieved on any or all DLLs.
Module 2 of 4
18
www.xilinx.com
1-800-255-7778
DS003-2 (v2.8.1) December 9, 2002
Product Specification