DS003-1 Datasheet, PDF (2/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
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Virtex Architecture
Virtex devices feature a flexible, regular architecture that
comprises an array of configurable logic blocks (CLBs) sur-
rounded by programmable input/output blocks (IOBs), all
interconnected by a rich hierarchy of fast, versatile routing
resources. The abundance of routing resources permits the
Virtex family to accommodate even the largest and most
complex designs.
Virtex FPGAs are SRAM-based, and are customized by
loading configuration data into internal memory cells. In
some modes, the FPGA reads its own configuration data
from an external PROM (master serial mode). Otherwise,
the configuration data is written into the FPGA (Select-
MAP™, slave serial, and JTAG modes).
The standard Xilinx Foundation™ and Alliance Series™
Development systems deliver complete design support for
Virtex, covering every aspect from behavioral and sche-
matic entry, through simulation, automatic design transla-
tion and implementation, to the creation, downloading, and
readback of a configuration bit stream.
Higher Performance
Virtex devices provide better performance than previous
generations of FPGA. Designs can achieve synchronous
system clock rates up to 200 MHz including I/O. Virtex
inputs and outputs comply fully with PCI specifications, and
interfaces can be implemented that operate at 33 MHz or 66
MHz. Additionally, Virtex supports the hot-swapping
requirements of Compact PCI.
Xilinx thoroughly benchmarked the Virtex family. While per-
formance is design-dependent, many designs operated
internally at speeds in excess of 100 MHz and can achieve
200 MHz. Table 2 shows performance data for representa-
tive circuits, using worst-case timing parameters.
Table 2: Performance for Common Circuit Functions
Function
Bits
Virtex -6
Register-to-Register
Adder
16
5.0 ns
64
7.2 ns
Pipelined Multiplier
8x8
16 x 16
5.1 ns
6.0 ns
Address Decoder
16
64
4.4 ns
6.4 ns
16:1 Multiplexer
5.4 ns
Parity Tree
9
4.1 ns
18
5.0 ns
36
6.9 ns
Chip-to-Chip
HSTL Class IV
200 MHz
LVTTL,16mA, fast slew
180 MHz
Module 1 of 4
2
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DS003-1 (v2.5 ) April 2, 2001
Product Specification