DS003-1 Datasheet, PDF (41/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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Virtex™ 2.5 V Field Programmable Gate Arrays
Virtex Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Input to Output Delay for LVTTL, 12 mA, Fast Slew Rate, with DLL
Speed Grade
Description
Symbol Device Min -6
-5
-4 Units
LVTTL Global Clock Input to Output Delay using T_ICKOFDLL XCV50 1.0 3.1 3.3 3.6 ns, max
Output Flip-flop, 12 mA, Fast Slew Rate, with DLL.
For data output with different standards, adjust
XCV100 1.0 3.1 3.3 3.6 ns, max
delays with the values shown in Output Delay
XCV150 1.0 3.1 3.3 3.6 ns, max
Adjustments.
XCV200 1.0 3.1 3.3 3.6 ns, max
XCV300 1.0 3.1 3.3 3.6 ns, max
XCV400 1.0 3.1 3.3 3.6 ns, max
XCV600 1.0 3.1 3.3 3.6 ns, max
XCV800 1.0 3.1 3.3 3.6 ns, max
XCV1000 1.0 3.1 3.3 3.6 ns, max
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see Table 2 and Table 3.
3. DLL output jitter is already included in the timing calculation.
Global Clock Input-to-Output Delay for LVTTL, 12 mA, Fast Slew Rate, without DLL
Speed Grade
Description
Symbol Device Min -6
-5
-4 Units
LVTTL Global Clock Input to Output Delay using
T_ICKOF XCV50 1.5 4.6 5.1 5.7 ns, max
Output Flip-flop, 12 mA, Fast Slew Rate, without DLL.
For data output with different standards, adjust
XCV100 1.5 4.6 5.1 5.7 ns, max
delays with the values shown in Input and Output
XCV150 1.5 4.7 5.2 5.8 ns, max
Delay Adjustments.
For I/O standards requiring V_REF, such as GTL,
GTL+, SSTL, HSTL, CTT, and AGO, an additional
XCV200 1.5 4.7 5.2 5.8 ns, max
XCV300 1.5 4.7 5.2 5.9 ns, max
600 ps must be added.
XCV400 1.5 4.8 5.3 6.0 ns, max
XCV600 1.6 4.9 5.4 6.0 ns, max
XCV800 1.6 4.9 5.5 6.2 ns, max
XCV1000 1.7 5.0 5.6 6.3 ns, max
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and
where all accessible IOB and CLB flip-flops are clocked by the global clock net.
2. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. The 35 pF load does not apply to the Min values.
For other I/O standards and different loads, see Table 2 and Table 3.
DS003-3 (v3.2) September 10, 2002
Production Product Specification
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1-800-255-7778
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