DS003-1 Datasheet, PDF(13/76 Page) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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DS003-1 Datasheet, PDF (13/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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Virtexâ¢ 2.5 V Field Programmable Gate Arrays

In addition to the test instructions outlined above, the

boundary-scan circuitry can be used to configure the

FPGA, and also to read back the configuration data.

Figure 10 is a diagram of the Virtex Series boundary scan

logic. It includes three bits of Data Register per IOB, the

IEEE 1149.1 Test Access Port controller, and the Instruction

Instruction Set

The Virtex Series boundary scan instruction set also

includes instructions to configure the device and read back

configuration data (CFG_IN, CFG_OUT, and JSTART). The

complete instruction set is coded as shown in Table 5.

Data Registers

The primary data register is the boundary scan register. For

each IOB pin in the FPGA, bonded or not, it includes three

bits for In, Out, and 3-State Control. Non-IOB pins have

appropriate partial bit population if input-only or output-only.

Each EXTEST CAPTURED-OR state captures all In, Out,

and 3-state pins.

The other standard data register is the single flip-flop

BYPASS register. It synchronizes data being passed

through the FPGA to the next downstream boundary scan

device.

The FPGA supports up to two additional internal scan

chains that can be specified using the BSCAN macro. The

macro provides two user pins (SEL1 and SEL2) which are

decodes of the USER1 and USER2 instructions respec-

tively. For these instructions, two corresponding pins (TDO1

and TDO2) allow user scan data to be shifted out of TDO.

Likewise, there are individual clock pins (DRCK1 and

DRCK2) for each user register. There is a common input pin

(TDI) and shared output pins that represent the state of the

TAP controller (RESET, SHIFT, and UPDATE).

Bit Sequence

The order within each IOB is: In, Out, 3-State. The

input-only pins contribute only the In bit to the boundary

scan I/O data register, while the output-only pins contributes

all three bits.

From a cavity-up view of the chip (as shown in EPIC), start-

ing in the upper right chip corner, the boundary scan

data-register bits are ordered as shown in Figure 11.

BSDL (Boundary Scan Description Language) files for Vir-

tex Series devices are available on the Xilinx web site in the

File Download area.

IOB IOB IOB IOB IOB

IOB.T

DATA IN

IOB

TDI

BYPASS

INSTRUCTION REGISTER

IOB

M TDO

IOB.I

IOB.Q

IOB.T

IOB.I

DATAOUT

SHIFT/

CAPTURE

CLOCK DATA

UPDATE

Figure 10: Virtex Series Boundary Scan Logic

EXTEST

X9016

DS003-2 (v2.8.1) December 9, 2002

Product Specification

www.xilinx.com

1-800-255-7778

Module 2 of 4

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