DS003-1 Datasheet, PDF (39/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
CLB SelectRAM Switching Characteristics
Description
Symbol
Min
Speed Grade
-6
-5
-4
Units
Sequential Delays
Clock CLK to X/Y outputs (WE active) 16 x 1 mode T_SHCKO16
1.2
2.3
2.6
3.0 ns, max
Clock CLK to X/Y outputs (WE active) 32 x 1 mode T_SHCKO32
1.2
2.7
3.1
3.5 ns, max
Shift-Register Mode
Clock CLK to X/Y outputs
Setup and Hold Times before/after Clock CLK⁽¹⁾
T_REG
1.2
3.7
4.1
4.7
Setup Time / Hold Time
ns, max
F/G address inputs
BX/BY data inputs (DIN)
CE input (WE)
Shift-Register Mode
T_AS/T_AH
T_DS/T_DH
T_WS/T_WH
0.25 / 0
0.34 / 0
0.38 / 0
0.5 / 0
0.7 / 0
0.8 / 0
0.6 / 0
0.8 / 0
0.9 / 0
0.7 / 0
0.9 / 0
1.0 / 0
ns, min
ns, min
ns, min
BX/BY data inputs (DIN)
CE input (WS)
Clock CLK
T_SHDICK
0.34
0.7
0.8
0.9 ns, min
T_SHCECK
0.38
0.8
0.9
1.0 ns, min
Minimum Pulse Width, High
T_WPH
1.2
2.4
2.7
3.1 ns, min
Minimum Pulse Width, Low
T_WPL
1.2
2.4
2.7
3.1 ns, min
Minimum clock period to meet address write cycle
time
T_WC
2.4
4.8
5.4
6.2 ns, min
Shift-Register Mode
Minimum Pulse Width, High
T_SRPH
1.2
2.4
2.7
3.1 ns, min
Minimum Pulse Width, Low
T_SRPL
1.2
2.4
2.7
3.1 ns, min
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
DS003-3 (v3.2) September 10, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
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