DS003-1 Datasheet, PDF (35/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
Clock Distribution Guidelines
Speed Grade
Description
Global Clock Skew⁽¹⁾
Device
Symbol
-6
-5
-4
Units
Global Clock Skew between IOB Flip-flops
XCV50
XCV100
T_GSKEWIOB
0.10 0.12 0.14
0.12 0.13 0.15
ns, max
ns, max
XCV150
0.12 0.13 0.15 ns, max
XCV200
0.13 0.14 0.16 ns, max
XCV300
0.14 0.16 0.18 ns, max
XCV400
0.13 0.13 0.14 ns, max
XCV600
0.14 0.15 0.17 ns, max
XCV800
0.16 0.17 0.20 ns, max
XCV1000
0.20 0.23 0.25 ns, max
Notes:
1. These clock-skew delays are provided for guidance only. They reflect the delays encountered in a typical design under worst-case
conditions. Precise values for a particular design are provided by the timing analyzer.
Clock Distribution Switching Characteristics
Description
GCLK IOB and Buffer
Global Clock PAD to output.
Global Clock Buffer I input to O output
Symbol
T_GPIO
T_GIO
Speed Grade
Min
-6
-5
-4
Units
0.33 0.7 0.8 0.9 ns, max
0.34 0.7 0.8 0.9 ns, max
DS003-3 (v3.2) September 10, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
Module 3 of 4
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