DS003-1 Datasheet, PDF (31/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
IOB Input Switching Characteristics Standard Adjustments
Description
Symbol
Standard⁽¹⁾
Min
Data Input Delay Adjustments
Standard-specific data input delay
adjustments
T_ILVTTL
T_ILVCMOS2
LVTTL
LVCMOS2
0
–0.02
T_{IPCI33_3} PCI, 33 MHz, 3.3 V –0.05
T_{IPCI33_5} PCI, 33 MHz, 5.0 V 0.13
T_{IPCI66_3} PCI, 66 MHz, 3.3 V –0.05
T_IGTL
GTL
0.10
T_IGTLP
GTL+
0.06
T_IHSTL
HSTL
0.02
T_ISSTL2
SSTL2
–0.04
T_ISSTL3
SSTL3
–0.02
T_ICTT
CTT
0.01
T_IAGP
AGP
–0.03
Notes:
1. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
Speed Grade
-6
-5
0
–0.04
–0.11
0.25
–0.11
0.20
0.11
0.03
–0.08
–0.04
0.02
–0.06
0
–0.04
–0.12
0.28
–0.12
0.23
0.12
0.03
–0.09
–0.05
0.02
–0.07
-4 Units
0
ns
–0.05 ns
–0.14 ns
0.33
ns
–0.14 ns
0.26
ns
0.14
ns
0.04
ns
–0.10 ns
–0.06 ns
0.02
ns
–0.08 ns
IOB Output Switching Characteristics
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays with the values shown in IOB Output Switching Characteristics Standard Adjustments, page 9.
Description
Propagation Delays
O input to Pad
O input to Pad via transparent latch
3-State Delays
T input to Pad high-impedance⁽¹⁾
T input to valid data on Pad
T input to Pad high-impedance via
transparent latch⁽¹⁾
T input to valid data on Pad via
transparent latch
GTS to Pad high impedance⁽¹⁾
Sequential Delays
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Symbol
T_IOOP
T_IOOLP
T_IOTHZ
T_IOTON
T_IOTLPHZ
T_IOTLPON
T_GTS
T_CH
T_CL
Speed Grade
Min
-6
-5
-4
Units
1.2
2.9
3.2
3.5 ns, max
1.4
3.4
3.7
4.0 ns, max
1.0
2.0
2.2
2.4 ns, max
1.4
3.1
3.3
3.7 ns, max
1.2
2.4
2.6
3.0 ns, max
1.6
3.5
3.8
4.2 ns, max
2.5
4.9
5.5
6.3 ns, max
0.8
1.5
1.7
2.0
ns, min
0.8
1.5
1.7
2.0
ns, min
DS003-3 (v3.2) September 10, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
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