DS003-1 Datasheet, PDF (14/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
Bit 0 ( TDO end)
Bit 1
Bit 2
Right half of Top-edge IOBs (Right-to-Left)
GCLK2
GCLK3
Left half of Top-edge IOBs (Right-to-Left)
Left-edge IOBs (Top-to-Bottom)
M1
M0
M2
Left half of Bottom-edge IOBs (Left-to-Right)
GCLK1
GCLK0
Right half of Bottom-edge IOBs (Left-to-Right)
DONE
PROG
Right-edge IOBs (Bottom -to-Top)
(TDI end) CCLK
990602001
Figure 11: Boundary Scan Bit Sequence
Table 5: Boundary Scan Instructions
Boundary-Scan
Command
Binary
Code(4:0)
Description
EXTEST
00000
Enables boundary-scan
EXTEST operation
SAMPLE/PRELOAD
00001
Enables boundary-scan
SAMPLE/PRELOAD
operation
USER 1
00010
Access user-defined
register 1
USER 2
00011
Access user-defined
register 2
CFG_OUT
00100
Access the configuration
bus for read operations.
CFG_IN
00101
Access the configuration
bus for write operations.
INTEST
00111
Enables boundary-scan
INTEST operation
USERCODE
01000
Enables shifting out
USER code
IDCODE
01001
Enables shifting out of ID
Code
HIGHZ
01010
3-states output pins while
enabling the Bypass
Register
JSTART
01100
Clock the start-up
sequence when
StartupClk is TCK
BYPASS
11111 Enables BYPASS
RESERVED
All other Xilinx reserved
codes instructions
Identification Registers
The IDCODE register is supported. By using the IDCODE,
the device connected to the JTAG port can be determined.
The IDCODE register has the following binary format:
vvvv:ffff:fffa:aaaa:aaaa:cccc:cccc:ccc1
where
v = the die version number
f = the family code (03h for Virtex family)
a = the number of CLB rows (ranges from 010h for XCV50
to 040h for XCV1000)
c = the company code (49h for Xilinx)
The USERCODE register is supported. By using the USER-
CODE, a user-programmable identification code can be
loaded and shifted out for examination. The identification
code is embedded in the bitstream during bitstream gener-
ation and is valid only after configuration.
Table 6: IDCODEs Assigned to Virtex FPGAs
FPGA
IDCODE
XCV50
v0610093h
XCV100
v0614093h
XCV150
v0618093h
XCV200
v061C093h
XCV300
v0620093h
XCV400
v0628093h
XCV600
v0630093h
XCV800
v0638093h
XCV1000
v0640093h
Including Boundary Scan in a Design
Since the boundary scan pins are dedicated, no special ele-
ment needs to be added to the design unless an internal
data register (USER1 or USER2) is desired.
If an internal data register is used, insert the boundary scan
symbol and connect the necessary pins as appropriate.
Development System
Virtex FPGAs are supported by the Xilinx Foundation and
Alliance CAE tools. The basic methodology for Virtex design
consists of three interrelated steps: design entry, imple-
mentation, and verification. Industry-standard tools are
used for design entry and simulation (for example, Synop-
sys FPGA Express), while Xilinx provides proprietary archi-
tecture-specific tools for implementation.
The Xilinx development system is integrated under the Xil-
inx Design Manager (XDM™) software, providing designers
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DS003-2 (v2.8.1) December 9, 2002
Product Specification