DS003-1 Datasheet, PDF (33/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

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Virtex™ 2.5 V Field Programmable Gate Arrays
IOB Output Switching Characteristics Standard Adjustments
Output delays terminating at a pad are specified for LVTTL with 12 mA drive and fast slew rate. For other standards, adjust
the delays by the values shown.
Description
Symbol
Standard ⁽¹⁾
Speed Grade
Unit
Min
-6
-5
-4
s
Output Delay Adjustments
Standard-specific adjustments for
T_{OLVTTL_S2} LVTTL, Slow, 2 mA
4.2
14.7 15.8 17.0
ns
output delays terminating at pads
(based on standard capacitive load,
T_{OLVTTL_S4}
4 mA
2.5
7.5
8.0
8.6
ns
Csl)
T_{OLVTTL_S6}
6 mA
1.8
4.8
5.1
5.6
ns
T_{OLVTTL_S8}
8 mA
1.2
3.0
3.3
3.5
ns
T_{OLVTTL_S12}
12 mA
1.0
1.9
2.1
2.2
ns
T_{OLVTTL_S16}
16 mA
0.9
1.7
1.9
2.0
ns
T_{OLVTTL_S24}
24 mA
0.8
1.3
1.4
1.6
ns
T_{OLVTTL_F2} LVTTL, Fast, 2mA
1.9
13.1 14.0 15.1
ns
T_{OLVTTL_F4}
4 mA
0.7
5.3
5.7
6.1
ns
T_{OLVTTL_F6}
6 mA
0.2
3.1
3.3
3.6
ns
T_{OLVTTL_F8}
8 mA
0.1
1.0
1.1
1.2
ns
T_{OLVTTL_F12}
12 mA
0
0
0
0
ns
T_{OLVTTL_F16}
16 mA
–0.10 –0.05 –0.05 –0.05 ns
T_{OLVTTL_F24}
24 mA
–0.10 –0.20 –0.21 –0.23 ns
T_OLVCMOS2
LVCMOS2
0.10 0.10 0.11 0.12 ns
T_{OPCI33_3} PCI, 33 MHz, 3.3 V 0.50
2.3
2.5
2.7
ns
T_{OPCI33_5} PCI, 33 MHz, 5.0 V 0.40
2.8
3.0
3.3
ns
T_{OPCI66_3} PCI, 66 MHz, 3.3 V 0.10 –0.40 –0.42 –0.46 ns
T_OGTL
GTL
0.6 0.50 0.54 0.6
ns
T_OGTLP
GTL+
0.7
0.8
0.9
1.0
ns
T_{OHSTL_I}
HSTL I
0.10 –0.50 –0.53 –0.5 ns
T_{OHSTL_III}
HSTL III
–0.10 –0.9 –0.9 –1.0 ns
T_{OHSTL_IV}
HSTL IV
–0.20 –1.0 –1.0 –1.1 ns
T_{OSSTL2_I}
SSTL2 I
–0.10 –0.50 –0.53 –0.5 ns
T_{OSSLT2_II}
SSTL2 II
–0.20 –0.9 –0.9 –1.0 ns
T_{OSSTL3_I}
SSTL3 I
–0.20 –0.50 –0.53 –0.5 ns
T_{OSSTL3_II}
SSTL3 II
–0.30 –1.0 –1.0 –1.1 ns
T_OCTT
CTT
0
–0.6 –0.6 –0.6 ns
T_OAGP
AGP
0
–0.9 –0.9 –1.0 ns
Notes:
1. Output timing is measured at 1.4 V with 35 pF external capacitive load for LVTTL. For other I/O standards and different loads, see
Table 2 and Table 3.
DS003-3 (v3.2) September 10, 2002
Production Product Specification
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