DS003-1 Datasheet, PDF (30/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

Virtex™ 2.5 V Field Programmable Gate Arrays
R
Speed Grade
Description
Device
Symbol
Min
-6
-5
-4
Units
Setup and Hold Times with respect to Clock CLK at IOB input
register⁽¹⁾
Setup Time / Hold Time
Pad, no delay
Pad, with delay
All
XCV50
XCV100
T_IOPICK/T_IOICKP
T_IOPICKD/T_IOICKPD
0.8 / 0
1.9 / 0
1.9 / 0
1.6 / 0
3.7 / 0
3.7 / 0
1.8 / 0
4.1 / 0
4.1 / 0
2.0 / 0
4.7 / 0
4.7 / 0
ns, min
ns, min
ns, min
XCV150
1.9 / 0 3.8 / 0 4.3 / 0 4.9 / 0 ns, min
XCV200
2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min
XCV300
2.0 / 0 3.9 / 0 4.4 / 0 5.0 / 0 ns, min
XCV400
2.1 / 0 4.1 / 0 4.6 / 0 5.3 / 0 ns, min
XCV600
2.1 / 0 4.2 / 0 4.7 / 0 5.4 / 0 ns, min
XCV800
2.2 / 0 4.4 / 0 4.9 / 0 5.6 / 0 ns, min
XCV1000
2.3 / 0 4.5 / 0 5.0 / 0 5.8 / 0 ns, min
ICE input
Set/Reset Delays
All
T_IOICECK/T_IOCKICE 0.37/ 0 0.8 / 0 0.9 / 0 1.0 / 0 ns, max
SR input (IFF, synchronous)
All
T_IOSRCKI
0.49
1.0
1.1
1.3 ns, max
SR input to IQ (asynchronous)
All
T_IOSRIQ
0.70
1.4
1.6
1.8 ns, max
GSR to output IQ
All
T_GSRQ
4.9
9.7
10.9
12.5 ns, max
Notes:
1. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed "best-case", but
if a "0" is listed, there is no positive hold time.
2. Input timing for LVTTL is measured at 1.4 V. For other I/O standards, see Table 3.
Module 3 of 4
6
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DS003-3 (v3.2) September 10, 2002
Production Product Specification