DS003-1 Datasheet, PDF (45/76 Pages) Xilinx, Inc – Fast, high-density Field-Programmable Gate Arrays

R
Virtex™ 2.5 V Field Programmable Gate Arrays
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.
Speed Grade
-6
-5
Description
Symbol Min Max Min Max
Input Clock Frequency (CLKDLLHF)
FCLKINHF 60 200 60 180
Input Clock Frequency (CLKDLL)
FCLKINLF 25 100 25
90
Input Clock Pulse Width (CLKDLLHF)
T_DLLPWHF
2.0
-
2.4
-
Input Clock Pulse Width (CLKDLL)
T_DLLPWLF
2.5
-
3.0
Notes:
1. All specifications correspond to Commercial Operating Temperatures (0°C to + 85°C).
-4
Min Max
60 180
25 90
2.4
-
3.0
-
Units
MHz
MHz
ns
ns
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
CLKDLLHF CLKDLL
Description
Input Clock Period Tolerance
Input Clock Jitter Tolerance (Cycle to Cycle)
Time Required for DLL to Acquire Lock
Symbol
F_CLKIN
Min Max Min Max Units
T_IPTOL
- 1.0 - 1.0 ns
T_IJITCC
- ± 150 - ± 300 ps
T_LOCK > 60 MHz
-
20
-
20
µs
50 - 60 MHz -
-
-
25
µs
40 - 50 MHz -
-
-
50
µs
30 - 40 MHz -
-
-
90
µs
25 - 30 MHz -
-
- 120 µs
Output Jitter (cycle-to-cycle) for any DLL Clock Output⁽¹⁾
Phase Offset between CLKIN and CLKO⁽²⁾
Phase Offset between Clock Outputs on the DLL⁽³⁾
T_OJITCC
T_PHIO
T_PHOO
± 60
± 100
± 140
± 60 ps
± 100 ps
± 140 ps
Maximum Phase Difference between CLKIN and
CLKO ⁽⁴⁾
T_PHIOM
± 160
± 160 ps
Maximum Phase Difference between Clock Outputs on
the DLL⁽⁵⁾
T_PHOOM
± 200
± 200 ps
Notes:
1. Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2. Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
3. Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4. Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5. Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
6. All specifications correspond to Commercial Operating Temperatures (0°C to +85°C).
DS003-3 (v3.2) September 10, 2002
Production Product Specification
www.xilinx.com
1-800-255-7778
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